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| ? copyright 2000 advanced micro devices, inc. all rights reserved. publication# 20732 rev: d amendment/ 0 issue date: june 2000 draft am186 and am188 high-performance, 80c186- and 80c188-compatible, 16-bit embedded microcontrollers with ram distinctive characteristics n e86 tm family 80c186- and 80c188-compatible microcontrollers with enhanced bus interface lower system cost with high performance 3.3-v 0.3-v operation with 5-v tolerant i/o n memory integration 32 kbyte of internal sram internal sram provides same performance as zero-wait-state external memory n high performance 25-, 33-, 40- and 50-mhz operating frequencies supports zero-wait-state operation at 50 mhz with 55-ns external memory 1-mbyte memory address space 64-kbyte i/o space n enhanced features provide faster access to memory and various clock input modes nonmultiplexed address bus provides glueless interface to external ram and rom phase-locked loop (pll) enables processor to operate at up to four times clock input frequency n enhanced integrated peripherals thirty-two programmable i/o (pio) pins asynchronous serial port allows full-duplex, 7-bit or 8-bit data transfers dma to and from asynchronous serial port synchronous serial interface allows half-duplex, bidirectional data transfer to and from asics reset configuration register additional external interrupts hardware watchdog timer can generate nmi or system reset pseudo static ram (psram) controller includes auto refresh capability n familiar 80c186 peripherals with enhanced functionality two independent dma channels programmable interrupt controller with six external interrupts three programmable 16-bit timers programmable memory and peripheral chip-select logic programmable wait state generator power-save clock mode n software-compatible with the 80c186 and 80c188 microcontrollers n widely available native development tools, applications, and system software n available in the following packages: 100-pin, thin quad flat pack (tqfp) 100-pin, plastic quad flat pack (pqfp) general description the am186 tm er and am188 tm er microcontrollers are part of the amd e86? family of embedded microcontrollers and microprocessors based on the x86 architecture. the AM186ER and am188er microcontrollers are the ideal upgrade for designs requiring 80c186/80c188 microcontroller compatibility, increased performance, serial communications, a direct bus interface, and integrated memory. the AM186ER and am188er microcontrollers integrate memory and the functions of the cpu, nonmultiplexed address bus, timers, chip selects, interrupt controller, dma controller, psram controller, watchdog timer, asynchronous serial port, synchronous serial interface, and programmable i/o (pio) pins on one chip. compared to the 80c186/ 80c188 microcontrollers, the AM186ER and am188er microcontrollers enable designers to reduce the size, power consumption, and cost of embedded systems, while increasing functionality and performance. the AM186ER and am188er microcontrollers have been designed to meet the most common requirements of embedded products developed for the communications, office automation, mass storage, and general embedded markets. specific applications include feature phones, cellular phones, pbxs, multiplexers, modems, disk drives, hand-held terminals and desktop terminals, fax machines, printers, photocopiers, and industrial controls. er tm tm er
2am186 tm er and am188 tm er microcontrollers data sheet draft am186 ?er microcontroller block diagram note: * all pio signals are shared with other physical pins. see the pin descriptions beginning on page 30 and table 3 on page 36 for information on shared functions. registers control s 2 interrupt control unit timer control unit dma unit bus interface unit execution unit chip-select unit clock and power management unit control registers 16-bit count registers max count a registers 16-bit count registers 20-bit destination pointers 20-bit source pointers control registers control registers control registers 01 (wdt)2 0 1 max count b registers refresh control unit control registers control registers control registers clkoutb clkouta int4 int3/inta 1/irq int2/inta 0 int1/select int0 tmrout0 tmrout1 drq0 drq1 v cc gnd tmrin0 tmrin1 ardy srdy dt/r den hold hlda asynchronous serial port synchronous serial interface txd rxd sclk sdata sden0 sden1 nmi a19Ca0 ad15Cad0 ale bhe /aden wr wlb whb rd res lcs /once 0 mcs 2Cmcs 0 pcs 6/a2 pcs 3Cpcs 0 pcs 5/a1 ucs /once 1 x2 x1 control registers psram control unit mcs 3/rfsh pio unit pio31C pio0* s6/ uzi / clksel 2 clksel 1 32 kbyte sram (16k x 16) s 1/imdis s 0/sren watchdog timer (wdt) am186 tm er and am188 tm er microcontrollers data sheet 3 draft am188 ?er microcontroller block diagram notes: * all pio signals are shared with other physical pins. see the pin descriptions beginning on page 30 and table 3 on page 36 for information on shared functions. 20-bit source pointers interrupt control unit timer control unit dma unit bus interface unit 32 kbyte sram (32k x 8) chip-select unit clock and power management control registers 16-bit count registers max count a registers 16-bit count registers 20-bit destination pointers control registers control registers control registers 01 (wdt)2 0 1 max count b registers refresh control unit control registers control registers control registers clkoutb clkouta int4 int3/inta 1/irq int2/inta 0 int1/select int0 tmrout0 tmrout1 drq0 drq1 v cc gnd tmrin0 tmrin1 asynchronous serial port synchronous serial interface txd rxd sclk sdata sden0 sden1 nmi a19Ca0 ad7Cad0 ale wr wb rd res lcs /once 0 mcs 2Cmcs 0 pcs 6/a2 pcs 3Cpcs 0 pcs 5/a1 ucs /once 1 x2 x1 control registers psram control unit mcs 3/rfsh pio unit pio31C pio0* control registers ao15Cao8 rfsh 2/aden execution unit ardy srdy dt/r den hold hlda s6/ uzi / clksel 2 clksel 1 s 1/imdis s 0/sren s 2 watchdog timer (wdt) 4am186 tm er and am188 tm er microcontrollers data sheet draft ordering information standard products amd standard products are available in several packages and operating ranges. the order numbers (valid combinations) are formed by a combination of the elements below. C25 = 25 mhz C33 = 33 mhz C40 = 40 mhz C50 = 50 mhz temperature range c = er commercial (t c =0 c to +100 c) i = er industrial (t a =C40 c to +85 c) where: t c = case temperature where: t a = ambient temperature speed option device number/description lead forming \w=trimmed and formed valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. valid combinations package type v=100-pin thin quad flat pack (tqfp) k=100-pin plastic quad flat pack (pqfp) AM186ER = high-performance, 80c186-compatible, 16-bit embedded microcontroller with ram am188er = high-performance, 80c188-compatible, 16-bit embedded microcontroller with ram C50 v c \w AM186ER valid combinations AM186ERC25 AM186ERC33 AM186ERC40 AM186ERC50 vc\w or kc\w am188erC25 am188erC33 am188erC40 am188erC50 vc\w or kc\w AM186ERC25 AM186ERC33 AM186ERC40 AM186ERC50 ki\w or vi\w am188erC25 am188erC33 am188erC40 am188erC50 ki\w or vi\w am186 tm er and am188 tm er microcontrollers data sheet 5 draft draft table of contents distinctive characteristics ................................................................................................... ......... 1 general description ........................................................................................................... .......... 1 am 186?er microcontroller block diagram ................................................................................ 2 am188?er microcontroller block diagram ................................................................................ 3 ordering information .......................................................................................................... .......... 4 list of figures ............................................................................................................... ............... 9 list of tables ................................................................................................................ ............... 9 revision history .............................................................................................................. ........... 10 e86? family of embedded microprocessors and microcontrollers .......................................... 12 related documents ....................................................................................................... 13 demonstration board products ...................................................................................... 13 third-party development support products ............................................................................13 customer service .......................................................................................................... 13 key features and benefits ..................................................................................................... ... 14 application considerations ............................................................................................ 14 comparison of the a m 186?er and 80c186 microcontrollers ................................................. 15 tqfp connection diagram and pinoutsa m 186?er microcontroller ................................... 16 tqfp pin assignmentsam186?er microcontroller (sorted by pin number) ...................... 17 tqfp pin assignmentsam186?er microcontroller (sorted by pin name) .......................... 18 tqfp connection diagram and pinoutsa m 188?er microcontroller ................................... 19 tqfp pin assignmentsam188?er microcontroller (sorted by pin number) ...................... 20 tqfp pin assignmentsa m 188?er microcontroller (sorted by pin name) ......................... 21 pqfp connection diagram and pinoutsa m 186?er microcontroller ................................... 22 pqfp pin assignmentsa m 186?er microcontroller (sorted by pin number) ...................... 23 pqfp pin assignmentsa m 186?er microcontroller (sorted by pin name) ......................... 24 pqfp connection diagram and pinoutsa m 188?er microcontroller ................................... 25 pqfp pin assignmentsa m 188?er microcontroller (sorted by pin number) ...................... 26 pqfp pin assignmentsa m 188?er microcontroller (sorted by pin name) ......................... 27 logic symbola m 186?er microcontroller ............................................................................. 28 logic symbola m 188?er microcontroller ............................................................................. 29 pin descriptions .............................................................................................................. ........... 30 pins used by emulators ................................................................................................. 30 a19Ca0 (a19/pio9, a18/pio8, a17/pio7) .................................................................... 30 ad7Cad0 ....................................................................................................................... 30 ad15Cad8 (am186?er microcontroller) ..................................................................... 30 ao15Cao8 (am188?er microcontroller) ..................................................................... 30 ale ........................................................................................................................... ..... 31 ardy .......................................................................................................................... ... 31 bhe /aden (am186?er microcontroller only) ............................................................ 31 clkouta ...................................................................................................................... 3 1 clkoutb ...................................................................................................................... 3 1 den /pio5 ...................................................................................................................... 31 drq1Cdrq0 (drq1/pio13, drq0/pio12) ................................................................. 32 dt/r /pio4 ..................................................................................................................... 32 gnd ........................................................................................................................... .... 32 hlda .......................................................................................................................... ... 32 hold .......................................................................................................................... ... 32 int0 .......................................................................................................................... ..... 32 int1/select ................................................................................................................ 32 int2/inta 0/pio31 ......................................................................................................... 33 int3/inta 1/irq ............................................................................................................. 33 int4/pio30 .................................................................................................................... 33 6am186 tm er and am188 tm er microcontrollers data sheet draft draft lcs /once 0 ................................................................................................................... 33 mcs 3/rfsh /pio25 ....................................................................................................... 33 mcs 2Cmcs 0 (mcs 2/pio24, mcs 1/pio15, mcs 0/pio14) .......................................... 34 nmi ........................................................................................................................... ..... 34 pcs 3Cpcs 0 (pcs 3/pio19, pcs 2/pio18, pcs 1/pio17, pcs 0/pio16) ...................... 34 pcs 5/a1/pio3 ............................................................................................................... 34 pcs 6/a2/pio2 ............................................................................................................... 34 pio31Cpio0 (shared) .................................................................................................... 35 rd .............................................................................................................................. .... 35 res .............................................................................................................................. .. 35 rfsh 2/aden (am188?er microcontroller only) ........................................................ 35 rxd/pio28 .................................................................................................................... 3 5 s 2 ............................................................................................................................. ...... 35 s 1/imdis ........................................................................................................................ 37 s 0/sren ........................................................................................................................ 37 s6/clksel 1/pio29 ....................................................................................................... 37 sclk/pio20 .................................................................................................................. 37 sdata/pio21 ................................................................................................................ 37 sden1/pio23, sden0/pio22 ....................................................................................... 37 srdy/pio6 .................................................................................................................... 3 8 tmrin0/pio11 .............................................................................................................. 38 tmrin1/pio0 ................................................................................................................ 38 tmrout0/pio10 .......................................................................................................... 38 tmrout1/pio1 ............................................................................................................ 38 txd/pio27 ..................................................................................................................... 38 ucs /once 1 .................................................................................................................. 38 uzi /clksel 2/pio26 ..................................................................................................... 38 v cc .............................................................................................................................. .. 39 whb (am186?er microcontroller only) ...................................................................... 39 wlb (am186?er microcontroller only) ........................................................................ 39 wb (am188?er microcontroller only) ......................................................................... 39 wr .............................................................................................................................. ... 39 x1 ............................................................................................................................ ....... 39 x2 ............................................................................................................................ ....... 39 functional description ........................................................................................................ ....... 40 memory organization ..................................................................................................... 40 i/o space ..................................................................................................................... .. 40 bus operation ................................................................................................................. ........... 41 bus interface unit ............................................................................................................ .......... 41 nonmultiplexed address bus ......................................................................................... 41 byte write enables ........................................................................................................ 41 output enable ................................................................................................................ 4 1 pseudo static ram (psram) support .......................................................................... 44 peripheral control block (pcb) ................................................................................................ .44 reading and writing the pcb ........................................................................................ 44 clock and power management .................................................................................................. 44 phase-locked loop (pll) ............................................................................................. 44 crystal-driven clock source .......................................................................................... 45 external source clock ................................................................................................... 45 system clocks ............................................................................................................... 48 power-save operation ................................................................................................... 48 initialization and processor reset .................................................................................. 48 reset configuration register ......................................................................................... 48 am186 tm er and am188 tm er microcontrollers data sheet 7 draft draft chip-select unit .............................................................................................................. ........... 49 chip-select timing ......................................................................................................... 49 ready and wait-state programming ............................................................................. 49 memory maps ................................................................................................................ 50 chip-select overlap ....................................................................................................... 51 upper memory chip select ............................................................................................ 51 low memory chip select ............................................................................................... 51 midrange memory chip selects ..................................................................................... 51 peripheral chip selects ................................................................................................. 52 internal memory ............................................................................................................... .......... 52 interaction with external ram ........................................................................................ 52 emulator and debug modes .......................................................................................... 52 refresh control unit .......................................................................................................... ........ 53 interrupt control unit ........................................................................................................ ......... 53 programming the interrupt control unit ......................................................................... 53 timer control unit ............................................................................................................ .......... 53 watchdog timer ................................................................................................................ ........ 54 direct memory access .......................................................................................................... ..... 54 dma operation .............................................................................................................. 55 asynchronous serial port/dma transfers ..................................................................... 55 dma channel control registers .................................................................................... 55 dma priority .................................................................................................................. .55 asynchronous serial port ...................................................................................................... .... 56 dma transfers through the serial port .......................................................................... 56 synchronous serial interface .................................................................................................. ... 56 four-pin interface .......................................................................................................... 57 programmable i/o (pio) pins ................................................................................................... .57 low-voltage operation ......................................................................................................... ..... 59 low-voltage standard ................................................................................................... 59 power savings ............................................................................................................... 59 input/output circuitry ..................................................................................................... 59 absolute maximum ratings ...................................................................................................... .60 operating ranges .............................................................................................................. ........ 60 dc characteristics over commercial and industrial operating ranges ................................... 60 thermal characteristics ....................................................................................................... ...... 61 tqfp package .............................................................................................................. 61 typical ambient temperatures ...................................................................................... 62 commercial and industrial switching characteristics and waveforms ...................................... 67 key to switching waveforms ......................................................................................... 67 alphabetical key to switching parameter symbols ....................................................... 68 numerical key to switching parameter symbols .......................................................... 69 switching characteristics over commercial and industrial operating ranges, read cycle (25 mhz and 33 mhz) ................................................................................ 70 switching characteristics over commercial and industrial operating ranges, read cycle (40 mhz and 50 mhz) ................................................................................ 71 read cycle waveforms ................................................................................................. 72 switching characteristics over commercial and industrial operating ranges, write cycle (25 mhz and 33 mhz) ................................................................................ 73 switching characteristics over commercial and industrial operating ranges, write cycle (40 mhz and 50 mhz) ................................................................................ 74 write cycle waveforms ................................................................................................. 75 switching characteristics over commercial and industrial operating ranges, internal ram show read cycle (25 mhz and 33 mhz) ................................................ 76 8am186 tm er and am188 tm er microcontrollers data sheet draft draft switching characteristics over commercial and industrial operating ranges, internal ram show read cycle (40 mhz and 50 mhz) ................................................ 76 internal ram show read cycle waveform ................................................................... 77 switching characteristics over commercial and industrial operating ranges, psram read cycle (25 mhz and 33 mhz) .................................................................. 78 switching characteristics over commercial and industrial operating ranges, psram read cycle (40 mhz and 50 mhz) .................................................................. 79 psram read cycle waveforms ................................................................................... 80 switching characteristics over commercial and industrial operating ranges, psram write cycle (25 mhz and 33 mhz) ................................................................... 81 switching characteristics over commercial and industrial operating ranges, psram write cycle (40 mhz and 50 mhz) ................................................................... 82 psram write cycle waveforms .................................................................................... 83 switching characteristics over commercial and industrial operating ranges, psram refresh cycle (25 mhz and 33 mhz) .............................................................. 84 switching characteristics over commercial and industrial operating ranges, psram refresh cycle (40 mhz and 50 mhz) .............................................................. 85 psram refresh cycle waveforms ............................................................................... 86 switching characteristics over commercial and industrial operating ranges, interrupt acknowledge cycle (25 mhz and 33 mhz) ..................................................... 87 switching characteristics over commercial operating ranges, interrupt acknowledge cycle (40 mhz and 50 mhz) ..................................................... 88 interrupt acknowledge cycle waveforms ...................................................................... 89 switching characteristics over commercial and industrial operating ranges, software halt cycle (25 mhz and 33 mhz) ................................................................... 90 switching characteristics over commercial and industrial operating ranges, software halt cycle (40 mhz and 50 mhz) ................................................................... 90 software halt cycle waveforms .................................................................................... 91 switching characteristics over commercial and industrial operating ranges, clock (25 mhz) .............................................................................................................. 92 switching characteristics over commercial and industrial operating ranges, clock (33 mhz) .............................................................................................................. 93 switching characteristics over commercial and industrial operating ranges, clock (40 mhz and 50 mhz) .......................................................................................... 94 clock waveformsactive mode ................................................................................... 95 clock waveformspower-save mode .......................................................................... 95 switching characteristics over commercial and industrial operating ranges, ready and peripheral timing (25 mhz and 33 mhz) .................................................... 96 switching characteristics over commercial and industrial operating ranges, ready and peripheral timing (40 mhz and 50 mhz) .................................................... 96 synchronous ready waveforms ................................................................................... 97 asynchronous ready waveforms .................................................................................. 97 peripheral waveforms ................................................................................................... 98 switching characteristics over commercial and industrial operating ranges, reset and bus hold (25 mhz and 33 mhz) ................................................................... 99 switching characteristics over commercial and industrial operating ranges, reset and bus hold (40 mhz and 50 mhz) ................................................................... 99 reset waveforms ........................................................................................................ 100 signals related to reset waveforms .......................................................................... 100 bus hold waveformsentering .................................................................................. 101 bus hold waveformsleaving ................................................................................... 101 switching characteristics over commercial and industrial operating ranges, synchronous serial interface (ssi) (25 mhz and 33 mhz) ......................................... 102 am186 tm er and am188 tm er microcontrollers data sheet 9 draft draft switching characteristics over commercial and industrial operating ranges, synchronous serial interface (ssi) (40 mhz and 50 mhz) ......................................... 102 synchronous serial interface (ssi) waveforms .......................................................... 103 tqfp physical dimensions ..................................................................................................... 1 04 pqfp physical dimensions ..................................................................................................... 1 05 index .......................................................................................................................... ......... index-1 list of figures figure 1. AM186ER 50-mhz example system design ......................................................... 15 figure 2. typical 80c186 system design ............................................................................. 15 figure 3. two-component address example ....................................................................... 40 figure 4. am186?er microcontroller address busnormal operation ............................. 42 figure 5. am186?er microcontrolleraddress bus disable in effect ............................... 42 figure 6. am188?er microcontroller address busnormal operation ............................. 43 figure 7. am188?er microcontrolleraddress bus disable in effect ............................... 43 figure 8. am186?er and am188?er microcontrollers oscillator configurations ............ 45 figure 9. peripheral control block register map .................................................................. 46 figure 10. clock organization ................................................................................................ 48 figure 11. ardy and srdy synchronization logic diagram ................................................ 49 figure 12. example memory maps ......................................................................................... 50 figure 13. dma unit block diagram ....................................................................................... 56 figure 14. synchronous serial interface multiple write .......................................................... 58 figure 15. synchronous serial interface multiple read .......................................................... 58 figure 16. thermal resistance ( c/watt) ............................................................................... 61 figure 17. thermal characteristics equations ........................................................................ 61 figure 18. typical ambient temperatures for pqfp with two-layer board .......................... 63 figure 19. typical ambient temperatures for tqfp with two-layer board .......................... 64 figure 20. typical ambient temperatures for pqfp with four-layer to six-layer board ..... 65 figure 21. typical ambient temperatures for tqfp with four-layer to six-layer board ..... 66 list of tables table 1. related amd productse86? family devices ................................................... 12 table 2. data byte encoding ............................................................................................... 31 table 3. numeric pio pin assignments .............................................................................. 36 table 4. alphabetic pio pin assignments ........................................................................... 36 table 5. bus cycle encoding ............................................................................................... 37 table 6. clocking modes ..................................................................................................... 39 table 7. segment register selection rules ........................................................................ 40 table 8. maximum and minimum clock frequencies .......................................................... 44 table 9. AM186ER microcontroller maximum dma transfer rates .................................. 55 table 10. thermal characteristics ( c/watt) ......................................................................... 61 table 11. typical power consumption calculation ............................................................... 62 table 12. junction temperature calculation ......................................................................... 62 table 13. typical ambient temperatures for pqfp with two-layer board .......................... 63 table 14. typical ambient temperatures for tqfp with two-layer board .......................... 64 table 15. typical ambient temperatures for pqfp with four-layer to six-layer board ..... 65 table 16. typical ambient temperatures for tqfp with four-layer to six-layer board ..... 66 10 am186 tm er and am188 tm er microcontrollers data sheet draft revision history date rev description feb. 2000 d replaced block diagrams on page 2 and page 3 with updated diagrams showing that the internal data bus interfaces via the biu and not ram. feb. 2000 d added new industrial parts for ordering information on page 4. feb. 2000 d updated product listings and customer service matter on page 12 and page 13. feb. 2000 d replaced figure 8 on page 45 (microcontroller oscillator configurations) with updated figure. feb. 2000 d updated several references to watchdog timer on page 54 to reflect that the wdt is inactive after reset, not active). feb. 2000 d provided a value for the tbd in the table entitled, dc characteristics over commercial and industrial operating ranges on page 60. feb. 2000 d updated table title and "min" values for no. 66 in the switching characteristics table, read cycle (40 mhz and 50 mhz) on page 71. feb. 2000 d updated table title and "max" values for no. 87 in the switching characteristics table, write cycle (40 mhz and 50 mhz) on page 74. feb. 2000 d updated table title and "min" value for no. 9 (50 mhz) in the switching characteristics table, internal ram show read cycle (40 mhz and 50 mhz) on page 76. feb. 2000 d updated table title and "min" values for no. 66 in the switching characteristics table, psram read cycle (40 mhz and 50 mhz) on page 79. feb. 2000 d updated table title and "max" value for no. 68 (40 mhz) in the switching characteristics table, psram write cycle (40 mhz and 50 mhz) on page 82. feb. 2000 d updated table title in the switching characteristics table, psram refresh cycle (40 mhz and 50 mhz) on page 85. feb. 2000 d updated table title in the switching characteristics table, software halt cycle (40 mhz and 50 mhz) on page 90. feb. 2000 d updated "min" and "max" values in the switching characteristics table, clock (33 mhz) on page 93. feb. 2000 d updated table title in the switching characteristics table, clock (40 mhz and 50 mhz) on page 94. feb. 2000 d updated table title in the switching characteristics table, ready and peripheral timing (40 mhz and 50 mhz) on page 96. feb. 2000 d updated table title in the switching characteristics table, reset and bus hold (40 mhz and 50 mhz) on page 99. feb. 2000 d updated table title in the switching characteristics table, synchronous serial interface (ssi) (40 mhz and 50 mhz) on page 102. feb. 2000 d in the table "switching characteristics over commercial and industrial operating ranges read cycle (40 mhz and 50 mhz)", row 9, column "50 mhz" - "min", the "0" is deleted. feb. 2000 d in the table "switching characteristics over commercial and industrial operating ranges read cycle (40 mhz and 50 mhz)", row 66, column "40 mhz" - "min", the value is changed. feb. 2000 d in the table "switching characteristics over commercial and industrial operating ranges read cycle (40 mhz and 50 mhz)", row 66, column "50 mhz" - "min", the value is changed. feb. 2000 d in the table "switching characteristics over commercial and industrial operating ranges psram write cycle (40 mhz and 50 mhz)", row 68, column "40 mhz" - "max", the value is changed. may 2000 d under key features and benefits on page 14, in the third bullet "enhanced functionality," the feature, "a psram controller" was added. may 2000 d under hold on page 32, the sentence, "a hold request is second only to dram or psram refresh requests in priority of activity requests received by the processor." is changed. am186 tm er and am188 tm er microcontrollers data sheet 11 draft may 2000 d under srdy/pio6 on page 38, the following sentence was added: "when srdy is configured as p106, the internal srdy signal is driven low." may 2000 d in table 8, maximum and minimum clock frequencies, on page 44, the values are changed in the cell of row "divide by 2" and column "x1/x2 min" and in the cell of row "divide by 2" and column "clkouta min". may 2000 d in switching characteristics over commercial and industrial operating ranges on page 93, max value in the number "36" row was changed to "33." may 2000 d in switching characteristics over commercial and industrial operating ranges on page 94, the value in "40 mhz max" for row number 36 was changed to "33." may 2000 d in synchronous ready waveforms on page 97, the diagram was changed. may 2000 d in asynchronous ready waveforms on page 97, the diagram was changed. may 2000 d in "bhe /aden ", on page 31, the second paragraph under aden was changed. may 2000 d in "uzi /clksel 2/pio26", on page 38, the paragraph description of uzi was changed. may 2000 d in read cycle waveforms on page 72, the uzi line in the diagram was changed. may 2000 d in write cycle waveforms on page 75, the uzi line in the diagram was changed. may 2000 d added the diagram, table 11, ardy and srdy synchronization logic diagram, on page 49. may 2000 d added an index. date rev description 12 am186 tm er and am188 tm er microcontrollers data sheet draft e86? family of embedded microprocessors and microcontrollers table 1. related amd productse86? family devices device 1 notes: 1. 186 = 16-bit microcontroller and 80c186-compatible (except where noted otherwise); 188 = 16-bit microcontroller with 8-bit external data bus and 80c188-compatible (except where noted otherwise); lv = low voltage description 80c186/80c188 16-bit microcontroller 80l186/80l188 low-voltage, 16-bit microcontroller am186?em/am188?em high-performance, 16-bit embedded microcontroller am186emlv/am188emlv high-performance, 16-bit embedded microcontroller am186es/am188es high-performance, 16-bit embedded microcontroller am186eslv/am188eslv high-performance, 16-bit embedded microcontroller am186ed high-performance, 80c186- and 80c188-compatible, 16-bit embedded microcontroller with 8- or 16-bit external data bus am186edlv high-performance, 80c186- and 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8- or 16-bit external data bus AM186ER/am188er high-performance, low-voltage, 16-bit embedded microcontroller with 32 kbyte of internal sram am186cc high-performance, 16-bit embedded communications controller am186ch high-performance, 16-bit embedded hdlc microcontroller am186cu high-performance, 16-bit embedded usb microcontroller lansc300 high-performance, highly integrated, low-voltage, 32-bit embedded microcontroller lansc310 high-performance, single-chip, 32-bit embedded pc/at-compatible microcontroller lansc400 high-performance, single-chip, low-power, pc/at-compatible microcontroller lansc410 high-performance, single-chip, pc/at-compatible microcontroller lansc520 high-performance, single-chip, 32-bit embedded microcontroller am386?sx high-performance, 32-bit embedded microprocessor with 16-bit external data bus am386?dx high-performance, 32-bit embedded microprocessor with 32-bit external data bus am486?dx high-performance, 32-bit embedded microprocessor with 32-bit external data bus am5 x 86? high-performance, 32-bit embedded microprocessor with 32-bit external data bus amd-k6?-2e high-performance, 32-bit embedded microprocessor with 64-bit external data bus and 3dnow!? technology am386 ? sx/dx microprocessors am486 ? dx microprocessor e86 ? family of embedded microprocessors and microcontrollers am186es and am188?em am188emlv microcontrollers am188er microprocessors 16- and 32-bit microcontrollers 16-bit microcontrollers amd-k6 ?-2e microprocessor am5 x 86? microprocessor am186cc communications controller am186?cu usb microcontroller am186ch hdlc microcontroller 80c186 and 80c188 microcontrollers am188es microcontrollers am186em and microcontrollers 80l186 and 80l188 microcontrollers am186emlv & microcontrollers am186eslv & am188eslv AM186ER and microcontrollers am186ed am186edlv microcontroller microcontroller lan?sc310 microcontroller lansc300 microcontroller lansc410 microcontroller lansc400 microcontroller lansc520 microcontroller am186 tm er and am188 tm er microcontrollers data sheet 13 draft related documents the following documents provide additional informa- tion regarding the AM186ER and am188er microcon- trollers. n AM186ER and am188er microcontrollers users manual , order #21684 n fusione86 sm catalog , order #19255 n making the most of the am186?er or am188?er microcontroller application note , order #21046 n using the 3.3-v am186?er or am188?er micro- controller in a 5-v system application note, order #21045 n comparing the am186?em and AM186ER micro- controllers technical bulletin (available only at www.amd.com/products/epd/techdocs. ) n the advantages of integrated ram technical bul- letin (available only at www.amd.com/products/ epd/techdocs. ) a full description of the AM186ER and am188er mi- crocontrollers registers and instructions is included in the AM186ER and am188er microcontrollers users manual listed above. to order literature, contact the nearest amd sales of- fice or call the literature center at one of the numbers listed on the back cover of this manual. in addition, all these documents are available in pdf form on the amd web site. to access the amd home page, go to www.amd.com. then follow the embedded processor link for information about e86 microcontrollers. demonstration board products the sd186er demonstration board product is a stand- alone, low-cost evaluation platform for the AM186ER microcontroller. the sd186er board demonstrates the basic proces- sor functionality and features of the AM186ER micro- controller and the simplicity of its system design. the sd186er demonstration board is designed with the am186/am188 expansion interface that provides ac- cess to the AM186ER microcontroller signals. the 104-pin expansion interface facilitates prototyping by enabling the demonstration board to be used as the minimal system core of a design. contact your local amd sales office for more information on demonstra- tion board availability and pricing. third-party development support products the fusione86 program of partnerships for applica- tion solutions provides the customer with an array of products designed to meet critical time-to-market needs. products and solutions available from the amd fusione86 partners include protocol stacks, emulators, hardware and software debuggers, board-level prod- ucts, and software development tools, among others. in addition, mature development tools and applications for the x86 platform are widely available in the general marketplace. customer service the amd customer service network includes u.s. of- fices, international offices, and a customer training cen- ter. expert technical assistance is available from the amd worldwide staff of field application engineers and factory support staff to answer e86 and comm86 fam- ily hardware and software development questions. hotline and world wide web support for answers to technical questions, amd provides e-mail support as well as a toll-free number for direct access to our corporate applications hotline. note: the support telephone numbers listed below are subject to change. for current telephone numbers, refer to www.amd.com/support/literature . the amd world wide web home page provides the latest product information, including technical informa- tion and data on upcoming product releases. in addi- tion, epd codekit software on the web site provides tested source code example applications. additional contact information is listed on the back of this datasheet. for technical support questions on all e86 and comm86 products, send e-mail to epd.sup- port@amd.com . world wide web home page to access the amd home page go to: www.amd.com . then follow the embedded processors link for infor- mation about e86 family and comm86? products. questions, requests, and input concerning amds www pages can be sent via e-mail to webmas- ter@amd.com . documentation and literature free information such as data books, users manuals, data sheets, application notes, the 14 am186 tm er and am188 tm er microcontrollers data sheet draft key features and benefits the AM186ER and am188er microcontrollers are higher-performance, highly integrated versions of the 80c186/80c188 microprocessors, offering a migration path that was previously unavailable. new peripherals, on-chip system interface logic, and 32 kbyte of internal memory on the AM186ER microcontroller reduce the cost of existing 80c186/80c188 designs. upgrading to the AM186ER microcontroller is an attractive solution for several reasons: n integrated sram 32 kbyte of internal sram en- sures a low-cost supply of memory and a smaller form factor for system designs. the internal mem- ory provides the same performance as external zero-wait-state sram devices. n 3.3-v operation with 5-v-tolerant i/o 3.3-v oper- ation provides much lower power consumption when compared to existing 5-v designs. plus, the AM186ER and am188er controllers accommodate current 5-v designs with 5-v-tolerant i/o drivers. n x86 software compatibility 80c186/80c188- compatible and upward-compatible with the other members of the amd e86 family. n enhanced performance the AM186ER and am188er microcontrollers increase the perfor- mance of 80c186/80c188 systems, and the non- multiplexed address bus offers faster, unbuffered access to commodity-speed, external memory. n enhanced functionality enhanced on-chip peripherals include an asynchronous serial port, up to 32 pios, a hardware watchdog timer, an additional interrupt pin, a synchronous serial interface, a psram controller, a 16-bit reset configuration register, and enhanced chip-select functionality. application considerations the integration enhancements of the AM186ER micro- controller provide a high-performance, low-system- cost solution for 16-bit embedded microcontroller de- signs. both multiplexed and nonmultiplexed address buses are available on the AM186ER and am188er microcontrollers. the nonmultiplexed address bus eliminates system-support logic ordinarily needed to interface with external memory devices, while the mul- tiplexed address/data bus maintains the value of previ- ously engineered, customer-specific peripherals and circuits within the upgraded design. figure 1 on page 15 illustrates an example system design that uses the integrated peripheral set to achieve high performance with reduced system cost. internal memory the 32-kbyte internal ram fulfills the memory require- ments for many embedded systems. these systems can take advantage of the increased reliability, smaller system form factor, decreased system power, stable ram supply, and lower system cost compared with buying external sram. the integrated ram also en- sures that an entire embedded system will not require requalification based on the short life cycles of external sram. additionally, for those systems using more ram than required because of the granularity of exter- nal ram, the AM186ER microcontroller provides a closer system match. clock generation the integrated clock generation circuitry of the AM186ER and am188er microcontrollers enables the processors to operate at up to four times the crystal fre- quency. the design in figure 1 achieves 50-mhz cpu operation while using a 12.5-mhz crystal. the clocking frequency function is controlled by an internal pll. the following modes are available (see figure 10 on page 48): n divide by twothe frequency of the fundamental clock is half the frequency of the crystal with the pll disabled. n times onethe frequency of the fundamental clock will be the same as the external crystal with the pll enabled. n times fourthe frequency of the fundamental clock is four times the frequency of the crystal with the pll enabled. the default mode is times four. memory interface the integrated memory controller logic of the AM186ER and am188er microcontrollers provides a direct address bus to memory devices. using an exter- nal address latch controlled by the address latch en- able (ale) signal is no longer necessary. individual byte-write-enable signals on the AM186ER and am188er microcontrollers eliminate the need for ex- ternal high/low byte-write-enable circuitry. the maxi- mum bank size programmable for the memory chip- select signals is increased to facilitate the use of high- density memory devices. the improved memory timing specifications for the AM186ER and am188er microcontrollers facilitate the use of external memory devices with 55-ns access times at 50-mhz cpu operation. as a result, overall system cost is significantly reduced as system design- ers are able to use commonly available memory tech- nology. am186 tm er and am188 tm er microcontrollers data sheet 15 draft direct memory interface example figure 1 illustrates the direct interface to memory of the AM186ER microcontroller. the a19Ca0 bus connects to the memory address inputs, the ad bus connects to the data inputs and outputs, and the chip selects con- nect to the memory chip-select inputs. figure 1 also shows an implementation of an rs-232 console or modem communications port. the rs-232- to-cmos voltage-level converter is required for the electrical interface with the external device. comparison of the am 186?er and 80c186 microcontrollers figure 1 shows an example system using a 50-mhz AM186ER microcontroller. figure 2 shows a compara- ble system implementation with an 80c186 microcon- troller. because of its superior integration, the AM186ER system does not require the support devices required on the 80c186 example system. in addition, the AM186ER microcontroller provides significantly better performance with its 50-mhz clock rate. figure 1. am186?er 50-mhz example system design figure 2. typical 80c186 system design x2 x1 rs-232 level converter txd rxd ucs wr rd we oe cs ad15Cad0 a19Ca0 serial port AM186ER microcontroller 12.5-mhz crystal address data 32 kbyte sram timer 0C2 int4Cint0 dma 0C1 clkouta 50 mhz am29f400 flash ucs wr we oe cs ad15Cad0 ale 40-mhz crystal address data timer 0C2 int3 dma 0C1 clkout 20 mhz x2 x1 sram we we address data oe cs rd lcs bhe a0 pa l latch pcs 0 latch serial port rs-232 level converter int2Cint0 pios am29f400 flash 16 am186 tm er and am188 tm er microcontrollers data sheet draft tqfp connection diagram and pinoutsam186?er microcontroller top side view100-pin thin quad flat pack (tqfp) notes: pin 1 is marked for orientation. gnd 6/a2 5/a1 3 2 ad0 1 ad8 2 ad1 3 ad9 4 ad2 5 ad10 6 ad3 7 ad11 8 ad4 9 ad12 10 ad5 11 12 ad13 13 ad6 14 15 ad14 16 ad7 17 ad15 18 19 20 txd 21 rxd 22 sdata 23 sden1 24 sden0 25 v cc 75 int4 74 73 72 71 70 nmi 69 srdy 68 hold 67 hlda 66 65 64 63 a0 62 a1 61 60 a2 59 a3 58 a4 57 a5 56 a6 55 a7 54 a8 53 a9 52 a10 51 a11 v cc 100 drq0 99 drq1 98 tmrin0 97 tmrout0 96 tmrout1 95 tmrin1 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 int0 78 int1/ 77 int2/ 76 int3/ v cc v cc 1 0 0 1/irq sclk 26 27 28 29 ale 30 ardy 31 32 33 34 35 x1 36 37 38 clkouta 39 40 41 a19 42 a18 43 44 a17 45 a16 46 a15 47 a14 48 a13 49 a12 50 x2 v cc clkoutb v cc /0 /1 2 3/ gnd gnd gnd gnd gnd whb wlb dt/r den mcs 0 mcs 1 bhe/aden wr rd s2 s1/imdis s0/sren inta inta select ucs once once pcs pcs pcs pcs pcs pcs mcs mcs rfsh res lcs s6/clksel 1 uzi /clksel 2 AM186ER microcontroller am186 tm er and am188 tm er microcontrollers data sheet 17 draft tqfp pin assignmentsam186?er microcontroller (sorted by pin number) pin no. name pin no. name pin no. name pin no. name 1 ad0 26 sclk/pio20 51 a11 76 int3/inta 1/irq 2 ad8 27 bhe /aden 52 a10 77 int2/inta 0 3 ad1 28 wr 53 a9 78 int1/select 4 ad9 29 rd 54 a8 79 int0 5 ad2 30 ale 55 a7 80 ucs/once 1 6 ad10 31 ardy 56 a6 81 lcs /once 0 7 ad3 32 s 2 57 a5 82 pcs 6/a2/pio2 8 ad11 33 s 1/imdis 58 a4 83 pcs 5/a1/pio3 9 ad4 34 s 0/sren 59 a3 84 v cc 10 ad12 35 gnd 60 a2 85 pcs 3/pio19 11 ad5 36 x1 61 v cc 86 pcs 2/pio18 12 gnd 37 x2 62 a1 87 gnd 13 ad13 38 v cc 63 a0 88 pcs 1/pio17 14 ad6 39 clkouta 64 gnd 89 pcs 0/pio16 15 v cc 40 clkoutb 65 whb 90 v cc 16 ad14 41 gnd 66 wlb 91 mcs 2 17 ad7 42 a19/pio9 67 hlda 92 mcs 3/rfsh 18 ad15 43 a18/pio8 68 hold 93 gnd 19 s6/cklsel 1/pio29 44 v cc 69 srdy/pio6 94 res 20 uzi /clksel 2/pio26 45 a17/pio7 70 nmi 95 tmrin1/pio0 21 txd 46 a16 71 dt/r /pio4 96 tmrout1/pio1 22 rxd 47 a15 72 den /pio5 97 tmrout0/pio10 23 sdata/pio21 48 a14 73 mcs 0/pio14 98 tmrin0/pio11 24 sden1/pio23 49 a13 74 mcs 1/pio15 99 drq1/pio13 25 sden0/pio22 50 a12 75 int4 100 drq0/pio12 18 am186 tm er and am188 tm er microcontrollers data sheet draft tqfp pin assignmentsam186?er microcontroller (sorted by pin name) pin name no. pin name no. pin name no. pin name no. a0 63 ad5 11 gnd 93 s 2 32 a1 62 ad6 14 hlda 67 s6/clksel 1/pio29 19 a2 60 ad7 17 hold 68 sclk/pio20 26 a3 59 ad8 2 int0 79 sdata/pio21 23 a4 58 ad9 4 int1/select 78 sden0/pio22 25 a5 57 ad10 6 int2/inta 0 77 sden1/pio23 24 a6 56 ad11 8 int3/inta 1/irq 76 srdy/pio6 69 a7 55 ad12 10 int4 75 tmrin0/pio11 98 a8 54 ad13 13 lcs /once 0 81 tmrin1/pio0 95 a9 53 ad14 16 mcs 0/pio14 73 tmrout0/pio10 97 a10 52 ad15 18 mcs 1/pio15 74 tmrout1/pio1 96 a11 51 ale 30 mcs 2 91 txd 21 a12 50 ardy 31 mcs 3/rfsh 92 ucs /once 1 80 a13 49 bhe /aden 27 nmi 70 uzi /clksel 2/pio26 20 a14 48 clkouta 39 pcs 0/pio16 89 v cc 15 a15 47 clkoutb 40 pcs 1/pio17 88 v cc 38 a16 46 den /pio5 72 pcs 2/pio18 86 v cc 44 a17/pio7 45 drq0/pio12 100 pcs 3/pio19 85 v cc 61 a18/pio8 43 drq1/pio13 99 pcs 5/a1/pio3 83 v cc 84 a19/pio9 42 dt/r/ pio4 71 pcs 6/a2/pio2 82 v cc 90 ad0 1 gnd 12 rd 29 whb 65 ad1 3 gnd 35 res 94 wlb 66 ad2 5 gnd 41 rxd 22 wr 28 ad3 7 gnd 64 s 0/sren 34 x1 36 ad4 9 gnd 87 s 1/imdis 33 x2 37 am186 tm er and am188 tm er microcontrollers data sheet 19 draft tqfp connection diagram and pinoutsam188?er microcontroller top side view100-pin thin quad flat pack (tqfp) notes: pin 1 is marked for orientation. gnd 6/a2 5/a1 3 2 ad0 1 ao8 2 ad1 3 ao9 4 ad2 5 ao10 6 ad3 7 ao11 8 ad4 9 ao12 10 ad5 11 12 ao13 13 ad6 14 15 ao14 16 ad7 17 ao15 18 19 20 txd 21 rxd 22 sdata 23 sden1 24 sden0 25 v cc 75 int4 74 73 72 71 70 nmi 69 srdy 68 hold 67 hlda 66 65 64 63 a0 62 a1 61 60 a2 59 a3 58 a4 57 a5 56 a6 55 a7 54 a8 53 a9 52 a10 51 a11 v cc 100 drq0 99 drq1 98 tmrin0 97 tmrout0 96 tmrout1 95 tmrin1 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 int0 78 int1/ 77 int2/ 76 int3/ v cc v cc 1 0 0 1/irq sclk 26 27 28 29 ale 30 ardy 31 32 33 34 35 x1 36 37 38 clkouta 39 40 41 a19 42 a18 43 44 a17 45 a16 46 a15 47 a14 48 a13 49 a12 50 x2 v cc clkoutb v cc /0 /1 2 3/ gnd gnd gnd gnd gnd gnd wb dt/r den mcs 0 mcs 1 rfsh2/aden wr rd s0/sren inta inta select ucs once once pcs pcs pcs pcs pcs pcs mcs mcs rfsh res lcs s6/clksel 1 uzi /clksel 2 s2 s1/imdis am188er microcontroller 20 am186 tm er and am188 tm er microcontrollers data sheet draft tqfp pin assignmentsam188?er microcontroller (sorted by pin number) pin no. name pin no. name pin no. name pin no. name 1 ad0 26 sclk/pio20 51 a11 76 int3/inta 1/irq 2 ao8 27 rfsh 2/aden 52 a10 77 int2/inta 0/pio31 3 ad1 28 wr 53 a9 78 int1/select 4 ao9 29 rd 54 a8 79 int0 5 ad2 30 ale 55 a7 80 ucs /once 1 6 ao10 31 ardy 56 a6 81 lcs /once 0 7 ad3 32 s 2 57 a5 82 pcs 6/a2/pio2 8 ao11 33 s 1/imdis 58 a4 83 pcs 5/a1/pio3 9 ad4 34 s 0/sren 59 a3 84 v cc 10 ao12 35 gnd 60 a2 85 pcs 3/pio19 11 ad5 36 x1 61 v cc 86 pcs 2/pio18 12 gnd 37 x2 62 a1 87 gnd 13 ao13 38 v cc 63 a0 88 pcs 1/pio17 14 ad6 39 clkouta 64 gnd 89 pcs 0/pio16 15 v cc 40 clkoutb 65 gnd 90 v cc 16 ao14 41 gnd 66 wb 91 mcs 2/pio24 17 ad7 42 a19/pio9 67 hlda 92 mcs 3/rfsh /pio25 18 ao15 43 a18/pio8 68 hold 93 gnd 19 s6/clksel 1/pio29 44 v cc 69 srdy/pio6 94 res 20 uzi /clksel 2/pio26 45 a17/pio7 70 nmi 95 tmrin1/pio0 21 txd/pio27 46 a16 71 dt/r/ pio4 96 tmrout1/pio1 22 rxd/pio28 47 a15 72 den /pio5 97 tmrout0/pio10 23 sdata/pio21 48 a14 73 mcs 0/pio14 98 tmrin0/pio11 24 sden1/pio23 49 a13 74 mcs 1/pio15 99 drq1/pio13 25 sden0/pio22 50 a12 75 int4/pio30 100 drq0/pio12 am186 tm er and am188 tm er microcontrollers data sheet 21 draft tqfp pin assignmentsam188?er microcontroller (sorted by pin name) pin name no. pin name no. pin name no. pin name no. a0 63 ad5 11 gnd 93 s 1/imdis 33 a1 62 ad6 14 hlda 67 s 2 32 a2 60 ad7 17 hold 68 s6/c lksel 1/pio29 19 a3 59 ale 30 int0 79 sclk/pio20 26 a4 58 ao8 2 int1/select 78 sdata/pio21 23 a5 57 ao9 4 int2/inta 0/pio31 77 sden0/pio22 25 a6 56 ao10 6 int3/inta 1/irq 76 sden1/pio23 24 a7 55 ao11 8 int4/pio30 75 srdy/pio6 69 a8 54 ao12 10 lcs /once 0 81 tmrin0/pio11 98 a9 53 ao13 13 mcs 0/pio14 73 tmrin1/pio0 95 a10 52 ao14 16 mcs 1/pio15 74 tmrout0/pio10 97 a11 51 ao15 18 mcs 2/pio24 91 tmrout1/pio1 96 a12 50 ardy 31 mcs 3/rfsh /pio25 92 txd/pio27 21 a13 49 clkouta 39 nmi 70 ucs /once 1 80 a14 48 clkoutb 40 pcs 0/pio16 89 uzi /clksel 2 20 a15 47 den /pio5 72 pcs 1/pio17 88 v cc 15 a16 46 drq0/pio12 100 pcs 2/pio18 86 v cc 38 a17/pio7 45 drq1/pio13 99 pcs 3/pio19 85 v cc 44 a18/pio8 43 dt/r /pio4 71 pcs 5/a1/pio3 83 v cc 61 a19/pio9 42 gnd 12 pcs 6/a2/pio2 82 v cc 84 ad0 1 gnd 35 rd 29 v cc 90 ad1 3 gnd 41 res 94 wb 66 ad2 5 gnd 64 rfsh 2/aden 27 wr 28 ad3 7 gnd 65 rxd/pio28 22 x1 36 ad4 9 gnd 87 s 0/sren 34 x2 37 22 am186 tm er and am188 tm er microcontrollers data sheet draft pqfp connection diagram and pinoutsam186?er microcontroller top side view100-pin plastic quad flat pack (pqfp) notes: pin 1 is marked for orientation. ad0 ad8 ad1 ad9 ad2 ad10 ad3 ad11 ad4 ad12 ad5 ad13 ad6 ad14 ad7 ad15 txd rxd sdata sden1 sden0 gnd gnd sclk ale ardy x1 clkouta a19 a18 a17 a16 a15 a14 a12 a13 x2 v cc clkoutb v cc gnd int4 dt/r nmi srdy hold hlda a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 v cc gnd tmrin0 tmrout0 tmrout1 tmrin1 int0 gnd gnd v cc s6/clksel1 drq1 drq0 v cc v cc AM186ER microcontroller 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 bhe /aden uzi/clksel2 whb wlb den mcs0 wr rd s 2 s 1/imdis s 0/sren mcs 1 int3/inta 1/irq int2/inta 0 int1/select ucs /once 1 lcs /once 0 pcs 6/a2 pcs 5/a1 pcs 3 pcs 2 pcs 1 pcs 0 mcs 2 mcs 3/rfsh res am186 tm er and am188 tm er microcontrollers data sheet 23 draft pqfp pin assignmentsam186?er microcontroller (sorted by pin number) pin no. name pin no. name pin no. name pin no. name 1 sden1/pio23 26 a13 51 mcs 1/pio15 76 drq1/pio13 2 sden0/pio22 27 a12 52 int4/pio30 77 drq0/pio12 3 sclk/pio20 28 a11 53 int3/inta 1/irq 78 ad0 4 bhe /aden 29 a10 54 int2/inta 0/pio31 79 ad8 5 wr 30 a9 55 int1/select 80 ad1 6 rd 31 a8 56 int0 81 ad9 7 ale 32 a7 57 ucs /once 1 82 ad2 8 ardy 33 a6 58 lcs /once 0 83 ad10 9 s 2 34 a5 59 pcs 6/a2/pio2 84 ad3 10 s 1/imdis 35 a4 60 pcs 5/a1/pio3 85 ad11 11 s 0/sren 36 a3 61 v cc 86 ad4 12 gnd 37 a2 62 pcs 3/pio19 87 ad12 13 x1 38 v cc 63 pcs 2/pio18 88 ad5 14 x2 39 a1 64 gnd 89 gnd 15 v cc 40 a0 65 pcs 1/pio17 90 ad13 16 clkouta 41 gnd 66 pcs 0/pio16 91 ad6 17 clkoutb 42 whb 67 v cc 92 v cc 18 gnd 43 wlb 68 mcs 2/pio24 93 ad14 19 a19/pio9 44 hlda 69 mcs 3/rfsh /pio25 94 ad7 20 a18/pio8 45 hold 70 gnd 95 ad15 21 v cc 46 srdy/pio6 71 res 96 s6/clksel 1/pio29 22 a17/pio7 47 nmi 72 tmrin1/pio0 97 uzi /clksel 2/pio26 23 a16 48 dt/r / pio4 73 tmrout1/pio1 98 txd/pio27 24 a15 49 den /pio5 74 tmrout0/pio10 99 rxd/pio28 25 a14 50 mcs 0/pio14 75 tmrin0/pio11 100 sdata/pio21 24 am186 tm er and am188 tm er microcontrollers data sheet draft pqfp pin assignmentsam186?er microcontroller (sorted by pin name) pin name no. pin name no. pin name no. pin name no. a0 40 ad5 88 gnd 89 s 2 9 a1 39 ad6 91 hlda 44 s6/clksel 1/pio29 96 a2 37 ad7 94 hold 45 sclk/pio20 3 a3 36 ad8 79 int0 56 sdata/pio21 100 a4 35 ad9 81 int1/select 55 sden0/pio22 2 a5 34 ad10 83 int2/inta 0/pio31 54 sden1/pio23 1 a6 33 ad11 85 int3/inta 1/irq 53 srdy/pio6 46 a7 32 ad12 87 int4/pio30 52 tmrin0/pio11 75 a8 31 ad13 90 lcs /once 0 58 tmrin1/pio0 72 a9 30 ad14 93 mcs 0/pio14 50 tmrout0/pio10 74 a10 29 ad15 95 mcs 1/pio15 51 tmrout1/pio1 73 a11 28 ale 7 mcs 2/pio24 68 txd/pio27 98 a12 27 ardy 8 mcs 3/rfsh /pio25 69 ucs /once 1 57 a13 26 bhe /aden 4 nmi 47 uzi /clksel 2/pio26 97 a14 25 clkouta 16 pcs 0/pio16 66 v cc 15 a15 24 clkoutb 17 pcs 1/pio17 65 v cc 21 a16 23 den /pio5 49 pcs 2/pio18 63 v cc 38 a17/pio7 22 drq0/pio12 77 pcs 3/pio19 62 v cc 61 a18/pio8 20 drq1/pio13 76 pcs 5/a1/pio3 60 v cc 67 a19/pio9 19 dt/r /pio4 48 pcs 6/a2/pio2 59 v cc 92 ad0 78 gnd 12 rd 6 whb 42 ad1 80 gnd 18 res 71 wlb 43 ad2 82 gnd 41 rxd/pio28 99 wr 5 ad3 84 gnd 64 s 0/sren 11 x1 13 ad4 86 gnd 70 s 1/imdis 10 x2 14 am186 tm er and am188 tm er microcontrollers data sheet 25 draft pqfp connection diagram and pinoutsam188?er microcontroller top side view100-pin plastic quad flat pack (pqfp) notes: pin 1 is marked for orientation. ad0 ad8 ad1 ad9 ad2 ad10 ad3 ad11 ad4 ad12 ad5 ad13 ad6 ad14 ad7 ad15 txd rxd sdata sden1 sden0 gnd gnd sclk ale ardy x1 clkouta a19 a18 a17 a16 a15 a14 a12 a13 x2 v cc clkoutb v cc gnd int4 dt/r nmi srdy hold hlda a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 v cc gnd tmrin0 tmrout0 tmrout1 tmrin1 int0 gnd gnd v cc s6/clksel drq1 drq0 v cc v cc am188er microcontroller 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 rfsh 2/aden 1 uzi/clksel2 gnd wb den mcs0 wr rd s 2 s 1/imdis s 0/sren mcs 1 int3/inta 1/irq int2/inta 0 int1/select ucs /once 1 lcs /once 0 pcs 6/a2 pcs 5/a1 pcs 3 pcs 2 pcs 1 pcs 0 mcs 2 mcs 3/rfsh res 26 am186 tm er and am188 tm er microcontrollers data sheet draft pqfp pin assignmentsam188?er microcontroller (sorted by pin number) pin no. name pin no. name pin no. name pin no. name 1 sden1/pio23 26 a13 51 mcs 1/pio15 76 drq1/pio13 2 sden0/pio22 27 a12 52 int4/pio30 77 drq0/pio12 3 sclk/pio20 28 a11 53 int3/inta 1/irq 78 ad0 4 rfsh 2/aden 29 a10 54 int2/inta 0/pio31 79 ao8 5 wr 30 a9 55 int1/select 80 ad1 6 rd 31 a8 56 int0 81 ao9 7 ale 32 a7 57 ucs /once 1 82 ad2 8 ardy 33 a6 58 lcs /once 0 83 ao10 9 s 2 34 a5 59 pcs 6/a2/pio2 84 ad3 10 s 1/imdis 35 a4 60 pcs 5/a1/pio3 85 ao11 11 s 0/sren 36 a3 61 v cc 86 ad4 12 gnd 37 a2 62 pcs 3/pio19 87 ao12 13 x1 38 v cc 63 pcs 2/pio18 88 ad5 14 x2 39 a1 64 gnd 89 gnd 15 v cc 40 a0 65 pcs 1/pio17 90 ao13 16 clkouta 41 gnd 66 pcs 0/pio16 91 ad6 17 clkoutb 42 gnd 67 v cc 92 v cc 18 gnd 43 wb 68 mcs 2/pio24 93 ao14 19 a19/pio9 44 hlda 69 mcs 3/rfsh /pio25 94 ad7 20 a18/pio8 45 hold 70 gnd 95 ao15 21 v cc 46 srdy/pio6 71 res 96 s6/clksel 1/pio29 22 a17/pio7 47 nmi 72 tmrin1/pio0 97 uzi /clksel 2/pio26 23 a16 48 dt/r / pio4 73 tmrout1/pio1 98 txd/pio27 24 a15 49 den /pio5 74 tmrout0/pio10 99 rxd/pio28 25 a14 50 mcs 0/pio14 75 tmrin0/pio11 100 sdata/pio21 am186 tm er and am188 tm er microcontrollers data sheet 27 draft pqfp pin assignmentsam188?er microcontroller (sorted by pin name) pin name no. pin name no. pin name no. pin name no. a0 40 ad5 88 gnd 89 s 1/imdis 10 a1 39 ad6 91 hlda 44 s 2 9 a2 37 ad7 94 hold 45 s6/clksel 1/pio29 96 a3 36 ale 7 int0 56 sclk/pio20 3 a4 35 ao8 79 int1/select 55 sdata/pio21 100 a5 34 ao9 81 int2/inta 0/pio31 54 sden0/pio22 2 a6 33 ao10 83 int3/inta 1/irq 53 sden1/pio23 1 a7 32 ao11 85 int4/pio30 52 srdy/pio6 46 a8 31 ao12 87 lcs /once 0 58 tmrin0/pio11 75 a9 30 ao13 90 mcs 0/pio14 50 tmrin1/pio0 72 a10 29 ao14 93 mcs 1/pio15 51 tmrout0/pio10 74 a11 28 ao15 95 mcs 2/pio24 68 tmrout1/pio1 73 a12 27 ardy 8 mcs 3/rfsh /pio25 69 txd/pio27 98 a13 26 clkouta 16 nmi 47 ucs /once 1 57 a14 25 clkoutb 17 pcs 0/pio16 66 uzi /clksel 2/pio26 97 a15 24 den /pio5 49 pcs 1/pio17 65 v cc 15 a16 23 drq0/pio12 77 pcs 2/pio18 63 v cc 21 a17/pio7 22 drq1/pio13 76 pcs 3/pio19 62 v cc 38 a18/pio8 20 dt/r /pio4 48 pcs 5/a1/pio3 60 v cc 61 a19/pio9 19 gnd 12 pcs 6/a2/pio2 59 v cc 67 ad0 78 gnd 18 rd 6 v cc 92 ad1 80 gnd 41 res 71 wb 43 ad2 82 gnd 42 rfsh 2/aden 4 wr 5 ad3 84 gnd 64 rxd/pio28 99 x1 13 ad4 86 gnd 70 s 0/sren 11 x2 14 28 am186 tm er and am188 tm er microcontrollers data sheet draft logic symbolam186?er microcontroller notes: * these signals are the normal function of a pin that can be used as a pio. see the pin descriptions beginning on page 30 and table 3 on page 36 for information on shared function. ** all pio signals are shared with other physical pins. x1 x2 clkouta clkoutb a19Ca0 ad15Cad0 ale whb wlb rd wr s 2 hold hlda dt/r den ardy srdy tmrin0 tmrout0 sden1Csden0 sclk sdata 20 16 clocks address and address/data buses bus control timer control synchronous serial port control res int4 int3 / inta 1/irq int2 / inta 0 int1 / select int0 nmi pcs 6/a2 pcs 5/a1 pcs 3Cpcs 0 lcs /once 0 mcs 2Cmcs 0 ucs /once 1 drq1Cdrq0 txd rxd pio32Cpio0 4 reset control and interrupt service memory and peripheral control dma control asynchronous serial port control programmable i/o control 2 tmrin1 tmrout1 2 mcs 3/rfsh s6/clksel 1 bhe /aden uzi/clksel2 ** * * * * * * * * * * * * * * * * * * * * * * * 32 shared s 1/imdis s 0/sren 3 am186 tm er and am188 tm er microcontrollers data sheet 29 draft logic symbolam188?er microcontroller notes: * these signals are the normal function of a pin that can be used as a pio. see the pin descriptions beginning on page 30 and table 3 on page 36 for information on shared function. ** all pio signals are shared with other physical pins. x1 x2 clkouta clkoutb ao15Cao8 ad7Cad0 s6/clksel 1 ale rfsh 2/aden rd wr hold hlda dt/r den ardy srdy tmrin0 tmrout0 sden1Csden0 sclk sdata 8 8 clocks address and address/data buses bus control timer control synchronous serial port control res int4 int3 / inta 1/irq int2 / inta 0 int1 / select int0 nmi pcs 6/a2 pcs 5/a1 pcs 3Cpcs 0 lcs /once 0 mcs 2Cmcs 0 ucs /once 1 drq1Cdrq0 txd rxd pio31Cpio0 4 32 shared reset control and interrupt service memory and peripheral control dma control asynchronous serial port control programmable i/o control 2 uzi/clksel2 tmrin1 tmrout1 3 2 mcs 3/rfsh a19Ca0 20 wb ** * * * * * * * * * * * * * * * * * * * * * * * s 2 s 1/imdis s 0/sren 30 am186 tm er and am188 tm er microcontrollers data sheet draft pin descriptions pins used by emulators the following pins are used by emulators: a19 Ca0, ao15Cao8, ad7Cad0, ale, bhe /aden (on the AM186ER microcontroller), clkouta, rfsh 2/aden (on the am188er microcontroller), rd , s 2, s 1/imdis , s 0/sren , s6/clksel 1, and uzi /clksel 2. emulators require that s6/clksel 1 and uzi / clksel 2 be configured in their normal functionality, that is, as s6 and uzi . if bhe /aden (on the AM186ER microcontroller) or rfsh 2/aden (on the am188er microcontroller) is held low during the rising edge of res , s6 and uzi are configured in their normal func- tionality and cannot be programmed as pios. a19Ca0 (a19/pio9, a18/pio8, a17/pio7) address bus (output, three-state, synchronous) these pins supply nonmultiplexed memory or i/o ad- dresses to the system one-half of a clkouta period earlier than the multiplexed address and data bus (ad15Cad0 on the AM186ER microcontroller or ao15Cao8 and ad7Cad0 on the am188er microcon- troller). during a bus hold or reset condition, the ad- dress bus is in a high-impedance state. ad7Cad0 address and data bus (input/output, three-state, synchronous, level-sensitive) these time-multiplexed pins supply partial memory or i/o addresses, as well as data, to the system. ad7C ad0 supply the low-order 8 bits of an address to the system during the first period of a bus cycle (t 1 ). on a write, these pins supply data to the system during the remaining periods of that cycle (t 2 , t 3 , and t 4 ). on a read, these pins latch data at the end of t 3 . also, if s0 /sren (show read enable) was pulled low during reset or if the sr bit is set in the internal memory chip select (imcs) register, these pins supply the data read from internal memory during t 3 and t 4 . on the AM186ER microcontroller, ad7Cad0 combine with ad15Cad8 to form a complete multiplexed ad- dress and 16-bit data bus. on the am188er microcontroller, ad7Cad0 combine with ao15Cao8 to form a complete multiplexed ad- dress bus while ad7Cad0 is the 8-bit data bus. the address phase of these pins can be disabled. see the aden description with the bhe /aden pin. when wlb is negated, these pins are three-stated during t 2 , t 3 , and t 4 . during a bus hold or reset condition, the address and data bus are in a high-impedance state. during a power-on reset, the address and data bus pins (ad15Cad0 for the AM186ER microcontroller, ao15Cao8 and ad7Cad0 for the am188er microcon- troller) can also be used to load system configuration information into the internal reset configuration regis- ter. the system information is latched on the rising edge of res . ad15Cad8 (am186?er microcontroller) address and data bus (input/output, three-state, synchronous, level-sensitive) these time-multiplexed pins supply partial memory or i/o addresses, as well as data, to the system. ad15C ad8 supply the high-order 8 bits of an address to the system during the first period of a bus cycle (t 1 ). on a write, these pins supply data to the system during the remaining periods of that cycle (t 2 , t 3 , and t 4 ). on a read, these pins latch data at the end of t 3 . also, if s0 /sren (show read enable) was pulled low during reset or if the sr bit is set in the internal memory chip select (imcs) register, these pins supply the data read from internal memory during t 3 and t 4 . on the AM186ER microcontroller, ad15Cad8 combine with ad7Cad0 to form a complete multiplexed address and 16-bit data bus. the address phase of these pins can be disabled. see the aden description with the bhe /aden pin. when whb is negated, these pins are three-stated during t 2 , t 3 , and t 4. during a bus hold or reset condition, the address and data bus is in a high-impedance state. during a power-on reset, the address and data bus pins (ad15Cad0 for the AM186ER microcontroller, ao15Cao8 and ad7Cad0 for the am188er microcon- troller) can also be used to load system configuration information into the internal reset configuration regis- ter. the system information is latched on the rising edge of res . ao15Cao8 (am188?er microcontroller) address-only bus (output, three-state, synchronous, level-sensitive) on the am188er microcontroller, the address-only bus (ao15Cao8) contains valid high-order address bits from bus cycles t 1 Ct 4 . these outputs are three-stated during a bus hold or reset. on the am188er microcontroller, ao15Cao8 combine with ad7Cad0 to form a complete multiplexed address bus while ad7Cad0 is the 8-bit data bus. on the am188er microcontroller during a power-on reset, the ao15Cao8 and ad7Cad0 pins can also be used to load system configuration information into an internal register for later use. am186 tm er and am188 tm er microcontrollers data sheet 31 draft ale address latch enable (output, synchronous) this pin indicates to the system that an address ap- pears on the address and data bus (ad15Cad0 for the AM186ER microcontroller or ao15Cao8 and ad7Cad0 for the am188er microcontroller). the ad- dress is guaranteed valid on the trailing edge of ale. this pin is three-stated during once mode. ardy asynchronous ready (input, asynchronous, level-sensitive) this pin indicates to the microcontroller that the ad- dressed memory space or i/o device will complete a data transfer. the ardy pin accepts a rising edge that is asynchronous to clkouta and is active high. the falling edge of ardy must be synchronized to clkouta. to always assert the ready condition to the microcontroller, tie ardy high. if the system does not use ardy, tie the pin low to yield control to srdy. bhe /aden (am186?er microcontroller only) bus high enable (three-state, output, synchronous) address enable (input, internal pullup) bhe during a memory access, this pin and the least- significant address bit (ad0 or a0) indicate to the sys- tem which bytes of the data bus (upper, lower, or both) participate in a bus cycle. the bhe /aden and ad0 pins are encoded as shown in table 2. bhe is asserted during t 1 and remains asserted through t 3 and t w . bhe does not need to be latched. bhe is three-stated during bus hold and reset condi- tions. on the AM186ER microcontroller, wlb and whb im- plement the functionality of bhe and ad0 for high and low byte write enables. table 2. data byte encoding bhe /aden also signals dram refresh cycles when using the multiplexed address and data (ad) bus. a re- fresh cycle is indicated when both bhe /aden and ad0 are high. during refresh cycles, the a bus and the ad bus are not guaranteed to provide the same address during the address phase of the ad bus cycle. for this reason, the a0 signal cannot be used in place of the ad0 signal to determine refresh cycles. psram re- freshes also provide an additional rfsh signal (see the mcs 3/rfsh pin description on page 33). aden if bhe /aden is held high or left floating dur- ing power-on reset, the address portion of the ad bus (ad15Cad0) is enabled or disabled during lcs and ucs bus cycles based on the da bit in the lmcs and umcs registers. if the da bit is set, the memory ad- dress is accessed on the a19Ca0 pins. this mode of operation reduces power consumption. for more infor- mation, see the bus operation section on page 41. there is a weak internal pullup resistor on bhe /aden so no external pullup is required. if bhe /aden is held low on power-on reset, the ad bus drives both addresses and data. changing the da bit of the lmcs and umcs registers will have no effect. (s6 and uzi also assume their normal functionality in this instance. the pio mode and direction registers cannot reconfigure these pins as pios. see table 3 on page 36.) the pin is sampled within three crystal clock cycles after the rising edge of res . bhe /aden is three-stated during bus holds and once mode. note: once the above modes are set, they can be changed only by resetting the processor. clkouta clock output a (output, synchronous) this pin supplies the internal clock to the system. de- pending on the value of the power-save control regis- ter (pdcon), clkouta operates at either the cpu fundamental frequency (which varies with the divide by two, times one, and times four clocking modes), the power-save frequency, or is three-stated (see figure 10 on page 48). clkouta remains active during reset and bus hold conditions. clkoutb clock output b (output, synchronous) this pin supplies a clock to the system. depending on the value of the power-save control register (pd- con), clkoutb operates at either the cpu funda- mental frequency (which varies with the divide by two, times one, and times four clocking modes), the power- save frequency, or is three-stated (see figure 10 on page 48). clkoutb remains active during reset and bus hold conditions. den /pio5 data enable (output, three-state, synchronous) this pin supplies an output enable to an external data- bus transceiver. den is asserted during memory, i/o, and interrupt acknowledge cycles. den is deasserted when dt/r changes state. den is three-stated during a bus hold or reset condition. bhe ad0 type of bus cycle 0 0 word transfer 0 1 high byte transfer (bits 15C8) 1 0 low byte transfer (bits 7C0) 1 1 refresh 32 am186 tm er and am188 tm er microcontrollers data sheet draft drq1Cdrq0 (drq1/pio13, drq0/pio12) dma requests (input, synchronous, level-sensitive) these pins indicate to the microcontroller that an exter- nal device is ready for dma channel 1 or channel 0 to perform a transfer. drq1Cdrq0 are level-triggered and internally synchronized. the drq signals are not latched and must remain ac- tive until serviced. dt/r /pio4 data transmit or receive (output, three-state, synchronous) this pin indicates which direction data should flow through an external data-bus transceiver. when dt/r is asserted high, the microcontroller transmits data. when this pin is deasserted low, the microcontroller receives data. dt/r is three-stated during a bus hold or reset condition. gnd ground the ground pins connect the system ground to the mi- crocontroller. hlda bus hold acknowledge (output, synchronous) when an external bus master requests control of the local bus (by asserting hold), the microcontroller completes the bus cycle in progress and then relin- quishes control of the bus to the external bus master by asserting hlda and floating den , rd , wr , s 2Cs 0, ad15Cad0, s6, a19Ca0, bhe , whb , wlb , and dt/r , and then driving the chip selects ucs , lcs , mcs 3C mcs 0, pcs 6Cpcs 5, and pcs 3Cpcs 0 high. when the external bus master has finished using the local bus, it indicates this to the microcontroller by deasserting hold. the microcontroller responds by deasserting hlda. if the microcontroller requires access to the bus (that is, for refresh), it will deassert hlda before the external bus master deasserts hold. the external bus master must be able to deassert hold and allow the micro- controller access to the bus. see the timing diagrams for bus hold on page 101. this pin is three-stated dur- ing once mode. hold bus hold request (input, synchronous, level-sensitive) this pin indicates to the microcontroller that an external bus master needs control of the local bus. for more in- formation, see the hlda pin description. the AM186ER and am188er microcontrollers hold latency time, the time between hold request and hold acknowledge, is a function of the activity occur- ring in the processor when the hold request is re- ceived. a hold request is second only to dram or psram refresh requests in priority of activity requests received by the processor. this implies that if a hold request is received just as a dma transfer begins, the hold latency can be as great as four bus cycles. this occurs if a dma word transfer operation is taking place (AM186ER microcontroller only) from an odd address to an odd address. this is a total of 16 clock cycles or more if wait states are required. in addition, if locked transfers are performed, the hold latency time is in- creased by the length of the locked transfer. int0 maskable interrupt request 0 (input, asynchronous) this pin indicates to the microcontroller that an inter- rupt request has occurred. if the int0 pin is not masked, the microcontroller transfers program execu- tion to the location specified by the int0 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally and can be edge-triggered or level-triggered. to guarantee in- terrupt recognition, the requesting device must con- tinue asserting int0 until the request is acknowledged. int1/select maskable interrupt request 1 (input, asynchronous) slave select (input, asynchronous) int1 this pin indicates to the microcontroller that an interrupt request has occurred. if int1 is not masked, the microcontroller transfers program execution to the location specified by the int1 vector in the microcon- troller interrupt vector table. interrupt requests are synchronized internally and can be edge-triggered or level-triggered. to guarantee in- terrupt recognition, the requesting device must con- tinue asserting int1 until the request is acknowledged. select when the microcontroller interrupt control unit is operating as a slave to an external master inter- rupt controller, this pin indicates to the microcontroller that an interrupt type appears on the address and data bus. the int0 pin must indicate to the microcontroller that an interrupt has occurred before the select pin indicates to the microcontroller that the interrupt type appears on the bus. am186 tm er and am188 tm er microcontrollers data sheet 33 draft int2/inta 0/pio31 maskable interrupt request 2 (input, asynchronous) interrupt acknowledge 0 (output, synchronous) int2 this pin indicates to the microcontroller that an interrupt request has occurred. if the int2 pin is not masked, the microcontroller transfers program execu- tion to the location specified by the int2 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally and can be edge-triggered or level-triggered. to guarantee in- terrupt recognition, the requesting device must con- tinue asserting int2 until the request is acknowledged. int2 becomes inta 0 when int0 is configured in cas- cade mode. inta0 when the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on int0. the periph- eral issuing the interrupt request must provide the mi- crocontroller with the corresponding interrupt type. int3/inta 1/irq maskable interrupt request 3 (input, asynchronous) interrupt acknowledge 1 (output, synchronous) slave interrupt request (output, synchronous) int3 this pin indicates to the microcontroller that an interrupt request has occurred. if the int3 pin is not masked, the microcontroller then transfers program ex- ecution to the location specified by the int3 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. to guarantee in- terrupt recognition, the requesting device must con- tinue asserting int3 until the request is acknowledged. int3 becomes inta 1 when int1 is configured in cas- cade mode. inta 1 when the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on int1. the periph- eral issuing the interrupt request must provide the mi- crocontroller with the corresponding interrupt type. irq when the microcontroller interrupt control unit is operating as a slave to an external master interrupt controller, this pin lets the microcontroller issue an in- terrupt request to the external master interrupt control- ler. int4/pio30 maskable interrupt request 4 (input, asynchronous) this pin indicates to the microcontroller that an inter- rupt request has occurred. if the int4 pin is not masked, the microcontroller then transfers program ex- ecution to the location specified by the int4 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally and can be edge-triggered or level-triggered. to guarantee in- terrupt recognition, the requesting device must con- tinue asserting int4 until the request is acknowledged. lcs /once 0 lower memory chip select (output, synchronous, internal pullup) once mode request 0 (input) lcs this pin indicates to the system that a memory access is in progress to the lower memory block. the size of the lower memory block is programmable up to 512 kbyte. lcs is held high during a bus hold condi- tion. once 0 during reset, this pin and once 1 indicate to the microcontroller the mode in which it should operate. once 0 and once 1 are sampled on the rising edge of res . if both pins are asserted low, the microcontroller enters once mode; otherwise, it operates normally. in once mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. to guarantee that the microcontroller does not inadvertently enter once mode, once 0 has a weak internal pullup resistor that is active only during reset. mcs 3/rfsh /pio25 midrange memory chip select 3 (output, synchronous, internal pullup) automatic refresh (output, synchronous) mcs 3 this pin indicates to the system that a memory access is in progress to the fourth region of the midrange memory block. the base address and size of the midrange memory block are programmable. mcs 3 is held high during a bus hold condition. in addition, this pin has a weak internal pullup resistor that is active during reset. rfsh this pin provides a signal timed for auto re- fresh to psram devices. it is only enabled to function as a refresh pulse when the psram mode bit is set in the lmcs register. an active low pulse is generated for 1.5 clock cycles with an adequate deassertion pe- riod to ensure that overall auto refresh cycle time is met. 34 am186 tm er and am188 tm er microcontrollers data sheet draft mcs 2Cmcs 0 (mcs 2/pio24, mcs 1/pio15, mcs 0/pio14) midrange memory chip selects (output, synchronous, internal pullup) these pins indicate to the system that a memory ac- cess is in progress to the corresponding region of the midrange memory block. the base address and size of the midrange memory block are programmable. mcs 2Cmcs 0 are held high during a bus hold condi- tion. in addition, they have weak internal pullup resis- tors that are active during reset. unlike the ucs and lcs chip selects, the mcs outputs assert with the mul- tiplexed ad address bus. nmi nonmaskable interrupt (input, synchronous, edge- sensitive) this pin indicates to the microcontroller that an inter- rupt request has occurred. the nmi signal is the high- est priority hardware interrupt and, unlike the int4C int0 pins, cannot be masked. the microcontroller al- ways transfers program execution to the location spec- ified by the nonmaskable interrupt vector in the microcontroller interrupt vector table when nmi is as- serted. although nmi is the highest priority interrupt source, it does not participate in the priority resolution process of the maskable interrupts. there is no bit associated with nmi in the interrupt in-service or interrupt request reg- isters. this means that a new nmi request can interrupt an executing nmi interrupt service routine. as with all hardware interrupts, the if (interrupt flag) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. however, if maskable in- terrupts are reenabled by software in the nmi interrupt service routine, via the sti instruction for example, an nmi currently in service will not have any effect on the priority resolution of maskable interrupt requests. for this reason, it is strongly advised that the interrupt ser- vice routine for nmi does not enable the maskable in- terrupts. an nmi transition from low to high is latched and syn- chronized internally, and it initiates the interrupt at the next instruction boundary. to guarantee that the inter- rupt is recognized, the nmi pin must be asserted for at least one clkouta period. because nmi is rising edge sensitive, holding the pin high during reset has no effect on program execution. pcs 3Cpcs 0 (pcs 3/pio19, pcs 2/pio18, pcs 1/pio17, pcs 0/pio16) peripheral chip selects (output, synchronous) these pins indicate to the system that a memory ac- cess is in progress to the corresponding region of the peripheral memory block (either i/o or memory ad- dress space). the base address of the peripheral memory block is programmable. pcs 3Cpcs 0 are held high during a bus hold condition. they are also held high during reset. pcs 4 is not available on the AM186ER and am188er microcontrollers. unlike the ucs /lcs chip selects, the pcs outputs as- sert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80c186/80c188 microcontrollers. pcs 5/a1/pio3 peripheral chip select 5 (output, synchronous) latched address bit 1 (output, synchronous) pcs 5 this pin indicates to the system that a memory access is in progress to the sixth region of the periph- eral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. pcs 5 is held high during a bus hold condition. it is also held high during reset. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. a1 when the ex bit in the mcs and pcs auxiliary register is 0, this pin supplies an internally latched ad- dress bit 1 to the system. during a bus hold condition, a1 retains its previously latched value. pcs 6/a2/pio2 peripheral chip select 6 (output, synchronous) latched address bit 2 (output, synchronous) pcs 6 this pin indicates to the system that a memory access is in progress to the seventh region of the pe- ripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. pcs 6 is held high during a bus hold condition or reset. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in earlier gen- erations of the am186/am188 microcontrollers. a2 when the ex bit in the mcs and pcs auxiliary register is 0, this pin supplies an internally latched ad- dress bit 2 to the system. during a bus hold condition, a2 retains its previously latched value. am186 tm er and am188 tm er microcontrollers data sheet 35 draft pio31Cpio0 (shared) programmable i/o pins (input/output, asynchronous, open-drain) the AM186ER and am188er microcontrollers provide 32 individually programmable i/o pins. each pio can be programmed with the following attributes: pio func- tion (enabled/disabled), direction (input/output), and weak pullup or pulldown. on the AM186ER and am188er microcontrollers, the internal pullup resistor has a value of approximately 100 kohms. the internal pulldown resistor has a value of approximately 100 kohms. the pins that are multiplexed with pio31Cpio0 are listed in table 3 and table 4 on page 36. after power-on reset, the pio pins default to various configurations. the column titled power-on reset sta- tus in table 3 and table 4 lists the defaults for the pios. the system initialization code must reconfigure any pios as required. if pio29 (s6/clksel 1) is to be used in input mode, the input device must not drive pio29 low during power- on reset. the pin defaults to a pio input with pullup, so it does not need to be driven high externally. the a19Ca17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address ffff0h. the dt/r , den , and srdy pins also default to normal operation on power-on reset. rd read strobe (output, synchronous, three-state) this pin indicates to the system that the microcontroller is performing a memory or i/o read cycle. rd is guar- anteed not to be asserted before the address and data bus is floated during the address-to-data transition. rd is three-stated during bus holds and once mode. res reset (input, asynchronous, level-sensitive) this pin requires the microcontroller to perform a reset. when res is asserted, the microcontroller immedi- ately terminates its present activity, clears its internal logic, and cpu control is transferred to the reset ad- dress ffff0h. res must be held low for at least 1 ms. res can be asserted asynchronously to clkouta be- cause res is synchronized internally. for proper initial- ization, v cc must be within specifications, and clkouta must be stable for more than four clkouta periods during which res is asserted. the microcontroller begins fetching instructions ap- proximately 6.5 clkouta periods after res is deas- serted. this input is provided with a schmitt trigger to facilitate power-on res generation via an rc network. rfsh 2/aden (am188?er microcontroller only) refresh 2 (three-state, output, synchronous) address enable (input, internal pullup) rfsh 2 asserted low to signify a dram refresh bus cycle. the use of rfsh 2/aden to signal a refresh is not valid when psram mode is selected. instead, the mcs 3/rfsh signal is provided to the psram. during reset, this pin is a pullup. this pin is three-stated during bus holds and once mode. aden if rfsh 2/aden is held high or left floating on power-on reset, the ad bus (ao15Cao8 and ad7Cad0) is enabled or disabled during the address portion of lcs and ucs bus cycles based on the da bit in the lmcs and umcs registers. if the da bit is set, the memory ad- dress is accessed on the a19Ca0 pins. this mode of op- eration reduces power consumption. for more information, see the bus operation section on page 41. there is a weak internal pullup resistor on rfsh 2/ aden so no external pullup is required. if rfsh 2/aden is held low on power-on reset, the ad bus drives both addresses and data. changing the da bit of the lmcs and umcs registers will have no effect. (s6 and uzi also assume their normal functionality in this instance. the pio mode and direction registers cannot reconfigure these pins as pios. see table 3 and table 4 on page 36.) the pin is sampled within three crystal clock cycles after the rising edge of res . rfsh 2/aden is three-stated during bus holds and once mode. note: once the above modes are set, they can be changed only by resetting the processor. rxd/pio28 receive data (input, asynchronous) this pin supplies asynchronous serial receive data from the system to the internal uart of the microcon- troller. s 2 bus cycle status (output, three-state, synchronous) s 2 this pin indicates to the system the type of bus cycle in progress. s 2 can be used as a logical memory or i/o indicator. s 2 C s 0 are three-stated during bus holds, hold acknowledges, and once mode. during reset, these pins are pullups. the s 2 C s 0 pins are en- coded as shown in table 5 on page 37. 36 am186 tm er and am188 tm er microcontrollers data sheet draft table 3. numeric pio pin assignments notes: 1. these pins are used by emulators. (emulators also use s 2Cs 0, res , nmi, clkouta, bhe , ale, ad15Cad0, and a16Ca0.) 2. these pins revert to normal operation if bhe /aden (AM186ER microcontroller) or rfsh 2/aden (am188er microcontroller) is held low during power-on reset. 3. when used as a pio, input with pullup option available. 4. when used as a pio, input with pulldown option available. table 4. alphabetic pio pin assignments notes: 1. these pins are used by emulators. (emulators also use s 2Cs 0, res , nmi, clkouta, bhe , ale, ad15Cad0, and a16Ca0.) 2. these pins revert to normal operation if bhe /aden (AM186ER microcontroller) or rfsh 2/aden (am188er microcontroller) is held low during power-on reset. 3. when used as a pio, input with pullup option available. 4. when used as a pio, input with pulldown option available. pio no. associated pin power-on reset status 0 tmrin1 input with pullup 1 tmrout1 input with pulldown 2 pcs 6/a2 input with pullup 3 pcs 5/a1 input with pullup 4 dt/r normal operation (3) 5 den normal operation (3) 6 srdy normal operation (4) 7 (1) a17 normal operation (3) 8 (1) a18 normal operation (3) 9 (1) a19 normal operation (3) 10 tmrout0 input with pulldown 11 tmrin0 input with pullup 12 drq0 input with pullup 13 drq1 input with pullup 14 mcs 0 input with pullup 15 mcs 1 input with pullup 16 pcs 0 input with pullup 17 pcs 1 input with pullup 18 pcs 2 input with pullup 19 pcs 3 input with pullup 20 sclk input with pullup 21 sdata input with pullup 22 sden0 input with pulldown 23 sden1 input with pulldown 24 mcs 2 input with pullup 25 mcs 3/rfsh input with pullup 26 (1,2) uzi /clksel 2 input with pullup 27 txd input with pullup 28 rxd input with pullup 29 (1,2) s6/clksel 1 input with pullup 30 int4 input with pullup 31 int2 input with pullup associated pin pio no. power-on reset status a17 (1) 7 normal operation (3) a18 (1) 8 normal operation (3) a19 (1) 9 normal operation (3) den 5 normal operation (3) drq0 12 input with pullup drq1 13 input with pullup dt/r 4 normal operation (3) int2 31 input with pullup int4 30 input with pullup mcs 0 14 input with pullup mcs 1 15 input with pullup mcs 2 24 input with pullup mcs 3/rfsh 25 input with pullup pcs 0 16 input with pullup pcs 1 17 input with pullup pcs 2 18 input with pullup pcs 3 19 input with pullup pcs 5/a1 3 input with pullup pcs 6/a2 2 input with pullup rxd 28 input with pullup s6/clksel 1 (1,2) 29 input with pullup sclk 20 input with pullup sdata 21 input with pullup sden0 22 input with pulldown sden1 23 input with pulldown srdy 6 normal operation (4) tmrin0 11 input with pullup tmrin1 0 input with pullup tmrout0 10 input with pulldown tmrout1 1 input with pulldown txd 27 input with pullup uzi /clksel 2 (1,2) 26 input with pullup am186 tm er and am188 tm er microcontrollers data sheet 37 draft s 1/imdis bus cycle status (output, three-state, synchronous) internal memory disable (input, internal pullup) s 1 this pin indicates to the system the type of bus cycle in progress. s 1 can be used as a data transmit or receive indicator. s 2Cs 0 are three-stated during bus holds, hold acknowledges, and once mode. during reset, these pins are pullups. the s 2Cs 0 pins are en- coded as shown in table 5. imdis if asserted during reset, this pin disables inter- nal memory. internal memory disable mode is provided for emulation and debugging purposes. s 0/sren bus cycle status (output, three-state, synchronous) show read enable (input, internal pullup) s0 this pin indicates to the system the type of bus cycle in progress. s 2Cs 0 are three-stated during bus holds, hold acknowledges, and once mode. during reset, these pins are pullups. the s 2Cs 0 pins are en- coded as shown in table 5. sren if asserted during reset, this pin enables data read from internal memory to be shown/driven on the ad15Cad0 bus. note that if a byte read is being shown, the unused byte will also be driven on the ad15Cad0 bus.this mode is provided for emulation and debug- ging purposes. table 5. bus cycle encoding s6/clksel 1/pio29 bus cycle status bit 6 (output, synchronous) clock select 1 (input, internal pullup) s6 during the second and remaining periods of a cycle (t 2 , t 3 , and t 4 ), this pin is asserted high to indicate a dma-initiated bus cycle. during a bus hold or reset condition, s6 is three-stated. clksel 1 the clocking mode of the AM186ER and am188er microcontrollers is controlled by uzi / clksel 2/pio26 and s6/clksel 1/pio29. both clksel 2 and clksel 1 are held high during power- on reset because of an internal pullup resistor. this is the default clocking modetimes four. if clksel 1 is held low during power-on reset, the chip enters the di- vide by two clocking mode where the fundamental clock is derived by dividing the external clock input by 2. if divide by two mode is selected, the pll is dis- abled. this pin is latched within three crystal clock cy- cles after the rising edge of res . refer to reset waveforms on page 100 and signals related to reset waveforms on page 100 to determine signal hold times. see table 6 on page 39 for more information on the clocking modes. if s6 is used as pio29 in input mode, the device driving pio29 must not drive the pin low during power-on reset. s6/clksel 1/pio29 defaults to a pio input with pullup, so the pin does not need to be driven high externally. sclk/pio20 serial clock (output, synchronous) this pin supplies the synchronous serial interface (ssi) clock to a slave device, allowing transmit and receive operations to be synchronized between the microcon- troller and the slave. sclk is derived from the micro- controller internal clock and then divided by 2, 4, 8, or 16 depending on register settings. an access to any of the ssr or ssd registers acti- vates sclk for eight sclk cycles (see figure 14 and figure 15 on page 58). when sclk is inactive, it is held high by the microcontroller. sclk is three-stated during once mode. sdata/pio21 serial data (input/output, synchronous) this pin transmits and receives synchronous serial in- terface (ssi) data to and from a slave device. when sdata is inactive, a weak keeper holds the last value of sdata on the pin. sden1/pio23, sden0/pio22 serial data enables (output, synchronous) these pins enable data transfers on port 1 and port 0 of the synchronous serial interface (ssi). the micro- controller asserts either sden1 or sden0 at the be- ginning of a transfer and deasserts it after the transfer is complete. when sden1Csden0 are inactive, they are held low by the microcontroller. sden1Csden0 are three-stated during once mode. s 2 s 1 s 0 bus cycle 0 0 0 interrupt acknowledge 0 0 1 read data from i/o 0 1 0 write data to i/o 0 1 1 halt 1 0 0 instruction fetch 1 0 1 read data from memory 1 1 0 write data to memory 1 1 1 none (passive) 38 am186 tm er and am188 tm er microcontrollers data sheet draft srdy/pio6 synchronous ready (input, synchronous, level-sensitive) this pin indicates to the microcontroller that the ad- dressed memory space or i/o device will complete a data transfer. the srdy pin accepts an active high input synchronized to clkouta. using srdy instead of ardy allows a relaxed system timing because of the elimination of the one-half clock period required to internally synchronize ardy. to al- ways assert the ready condition to the microcontroller, tie srdy high. if the system does not use srdy, tie the pin low to yield control to ardy. when srdy is config- ured as p106, the internal srdy signal is driven low. tmrin0/pio11 timer input 0 (input, synchronous, edge-sensitive) this pin supplies a clock or control signal to the internal microcontroller timer 0. after internally synchronizing a low-to-high transition on tmrin0, the microcontroller increments the timer. tmrin0 must be tied high if not being used. tmrin1/pio0 timer input 1 (input, synchronous, edge-sensitive) this pin supplies a clock or control signal to the internal microcontroller timer 1. after internally synchronizing a low-to-high transition on tmrin1, the microcontroller increments the timer. tmrin1 must be tied high if not being used. tmrout0/pio10 timer output 0 (output, synchronous) this pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. tmrout1/pio1 timer output 1 (output, synchronous) this pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. txd/pio27 transmit data (output, asynchronous) this pin supplies asynchronous serial transmit data to the system from the internal uart of the microcontrol- ler. ucs /once 1 upper memory chip select (output, synchronous) once mode request 1 (input, internal pullup) ucs this pin indicates to the system that a memory access is in progress to the upper memory block. the base address and size of the upper memory block are programmable up to 512 kbyte. ucs is held high dur- ing a bus hold condition. after power-on reset, ucs is asserted because the mi- crocontroller begins executing at ffff0h and the de- fault configuration for the ucs chip select is 64 kbyte from f0000h to fffffh. once 1 during reset, this pin and once 0 indicate to the microcontroller the mode in which it should operate. once 0 and once 1 are sampled on the rising edge of res . if both pins are asserted low, the microcontroller enters once mode. otherwise, it operates normally. in once mode, all pins assume a high-impedance state and remain in that state until a subsequent reset oc- curs. to guarantee the microcontroller does not inad- vertently enter once mode, once 1 has a weak internal pullup resistor that is active only during a reset. uzi /clksel 2/pio26 upper zero indicate (output, synchronous) uzi this pin lets the designer determine if an ac- cess to the interrupt vector table is in progress by oring it with bits 15C10 of the address and data bus (ad15Cad10 on the AM186ER microcontroller and ao15Cao10 on the am188er microcontroller). uzi is the logical and of the inverted a19Ca16 bits. uzi is not held throughout the cycle. uzi is asserted in the first period and deasserted in the second period of a bus cycle. uzi /clksel 2 is three-stated during bus holds and once mode. clksel 2 the clocking mode of the AM186ER and am188er microcontrollers is controlled by uzi / clksel 2/pio26 and s6/clksel 1/pio29 during re- set. both clksel 2 and clksel 1 are held high during power-on reset because of an internal pullup resistor. this is the default clocking modetimes four, which is used if neither clock select is asserted low during re- set. if clksel 2 is held low during power-on reset, the mi- crocontroller enters times one mode. this pin is latched within three crystal clock cycles after the rising edge of res . refer to reset waveforms on page 100 and signals related to reset waveforms on page 100 to determine signal hold times. note that clock selection must be stable four clock cycles prior to exiting reset (that is, res going high). see table 6 on page 39 for specifics on the clocking modes and how to specify them. uzi /clksel 2 is three-stated during bus holds and once mode. am186 tm er and am188 tm er microcontrollers data sheet 39 draft table 6. clocking modes v cc power supply (input) these pins supply power (+3.3 v) to the microcontrol- ler. whb (am186?er microcontroller only) write high byte (output, three-state, synchronous) this pin and wlb indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. in 80c186 designs, this information is pro- vided by bhe , ad0, and wr . however, by using whb and wlb , the standard system interface logic and ex- ternal address latch that were required are eliminated. whb is asserted with ad15Cad8. whb is the logical or of bhe and wr . during reset, this pin is a pullup. this pin is three-stated during bus holds and once mode. wlb (am186?er microcontroller only) wb (am188?er microcontroller only) write low byte (output, three-state, synchronous) write byte (output, three-state, synchronous) wlb this pin and whb indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. in 80c186 designs, this information is provided by bhe , ad0, and wr . however, by using whb and wlb , the standard system interface logic and external address latch that were required are elim- inated. wlb is asserted with ad7Cad0. wlb is the logical or of a0 and wr . this pin is three-stated during bus holds and once mode. wb on the am188er microcontroller, this pin indi- cates a write to the bus. wb uses the same early timing as the nonmultiplexed address bus. wb is associated with ad7Cad0. this pin is three-stated during bus holds and once mode. wr write strobe (output, synchronous) this pin indicates to the system that the data on the bus is to be written to a memory or i/o device. wr is three- stated during a bus hold or reset condition. x1 crystal input (input) this pin and the x2 pin provide connections for a fun- damental mode crystal used by the internal oscillator circuit. if providing an external clock source, connect the source to x1 and leave x2 unconnected. unlike the rest of the pins on the AM186ER and am188er micro- controllers, x1 is not 5-v tolerant and has a maximum input equal to v cc . x2 crystal output (output) this pin and the x1 pin provide connections for a fun- damental mode crystal used by the internal oscillator circuit. if providing an external clock source, connect the source to x1 and leave x2 unconnected. unlike the rest of the pins on the AM186ER and am188er micro- controllers, x2 is not 5-v tolerant. clksel 2clksel 1 clocking mode hh times four hl divide by two lh times one ll reserved 1 notes: 1. the reserved clocking mode should not be used. entering the reserved clocking mode may cause unpredictable system behavior. 40 am186 tm er and am188 tm er microcontrollers data sheet draft functional description the AM186ER and am188er microcontrollers are based on the architecture of the original am186 and am188 microcontrollers and they function in the en- hanced mode of the am186 and am188 microcontrol- lers. enhanced mode includes system features such as power-save control. each of the 8086, 8088, 80186, and 80188 microcon- trollers contains the same basic set of registers, in- structions, and addressing modes. the AM186ER and am188er microcontrollers are backward compatible with the 80c186/80c188 and am186/am188 micro- controllers. a full description of the AM186ER and am188er mi- crocontrollers registers and instructions is included in the AM186ER and am188er microcontrollers users manual , order #21684. memory organization memory is organized in sets of segments. each seg- ment is a linear contiguous sequence of 64k (2 16 ) 8-bit bytes. memory is addressed using a two-component address consisting of a 16-bit segment value and a 16- bit offset. the 16-bit segment values are contained in one of four internal segment registers (cs, ds, ss, or es). the physical address is calculated by shifting the segment value left by 4 bits and adding the 16-bit offset value to yield a 20-bit physical address (see figure 3). this allows for a 1-mbyte physical address size. all instructions that address operands in memory must specify the segment value and the 16-bit offset value. for speed and compact instruction encoding, the seg- ment register used for physical address generation is implied by the addressing mode used (see table 7). figure 3. two-component address example i/o space the i/o space consists of 64k 8-bit or 32k 16-bit ports. separate instructions (in, ins and out, outs) address the i/o space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the dx register. eight-bit port addresses are zero- extended such that a15Ca8 are low. table 7. segment register selection rules 1 2 a 4 0 0 0 0 2 2 1 2 a 6 2 1 2 a 4 0 0 2 2 segment base logical address shift left 4 bits physical address to memory 15 0 19 0 19 0 15 0 15 0 offset memory reference needed segment register used implicit segment selection rule instructions code (cs) instructions (including immediate data) local data data (ds) all data references stack stack (ss) all stack pushes and pops; any memory references that use bp register external data (global) extra (es) all string instruction references that use the di register as an index am186 tm er and am188 tm er microcontrollers data sheet 41 draft bus operation the industry-standard 80c186/80c188 microcontrol- lers use a multiplexed address and data (ad) bus. the address is present on the ad bus only during the t 1 clock phase. the AM186ER and am188er microcon- trollers continue to provide the multiplexed ad bus and, in addition, provide a nonmultiplexed address (a) bus. the a bus provides an address to the system for the complete bus cycle (t 1 Ct 4 ). for systems where power consumption is a concern, the address can be disabled from being driven on the ad bus on the AM186ER microcontroller and on the ad and ao buses on the am188er microcontroller during the normal address portion of the bus cycle for accesses to ucs and/or lcs address spaces. in this mode, the affected bus is placed in a high-impedance state during the address portion of the bus cycle. this feature is enabled through the da bits in the umcs and lmcs registers. when address disable is in effect, the number of signals that assert on the bus during all nor- mal bus cycles to the associated address space is re- duced, thus decreasing power consumption, reducing processor switching noise, and preventing bus conten- tion with memory devices and peripherals when oper- ating at high clock rates. on the am188er microcontroller, the address is driven on a015Ca08 during the data portion of the bus cycle, regardless of the setting of the da bits. if the aden pin is pulled low during processor reset, the value of the da bits in the umcs and lmcs regis- ters is ignored and the address is driven on the ad bus for all accesses, thus preserving the industry-standard 80c186 and 80c188 microcontrollers multiplexed ad- dress bus and providing support for existing emulation tools. figure 4 on page 42 shows the affected signals during a normal read or write operation for an AM186ER mi- crocontroller. the address and data will be multiplexed onto the ad bus. figure 5 on page 42 shows an AM186ER microcontrol- ler bus cycle when address bus disable is in effect. this results in having the ad bus operate in a nonmulti- plexed data-only mode. the a bus will have the ad- dress during a read or write operation. figure 6 on page 43 shows the affected signals during a normal read or write operation for an am188er micro- controller. the multiplexed address/data mode is com- patible with the 80c188 microcontrollers and might be used to take advantage of existing logic or peripherals. figure 7 on page 43 shows an am188er microcontrol- ler bus cycle when address bus disable is in effect. the address and data is not multiplexed. the ad7Cad0 signals will have only data on the bus, while the a bus will have the address during a read or write operation. the ao bus will also have the address during t 2 Ct 4 . bus interface unit the bus interface unit controls all accesses to external peripherals and memory devices. external accesses include those to memory devices, as well as those to memory-mapped and i/o-mapped peripherals and the peripheral control block. the AM186ER and am188er microcontrollers provide an enhanced bus interface unit with the following features: n a nonmultiplexed address bus n separate byte write enables for high and low bytes on the AM186ER microcontroller and a write enable on the am188er microcontroller n pseudo static ram (psram) support the standard 80c186/80c188 multiplexed address and data bus requires system interface logic and an ex- ternal address latch. on the AM186ER and am188er microcontrollers, new byte write enables, psram con- trol logic, and a new nonmultiplexed address bus can reduce design costs by eliminating this external logic. nonmultiplexed address bus the nonmultiplexed address bus (a19Ca0) is valid one- half clkouta cycle in advance of the address on the ad bus. when used in conjunction with the modified ucs and lcs outputs and the byte write enable sig- nals, the a19Ca0 bus provides a seamless interface to external sram, psram, and flash/eprom memory systems. byte write enables the AM186ER microcontroller provides the whb (write high byte) and wlb (write low byte) signals which act as byte write enables. the am188er micro- controller provides the wb (write byte) signal which acts as a write enable. whb is the logical and of bhe and wr . whb is low when both bhe and wr are low. wlb is the logical and of a0 and wr . wlb is low when a0 and wr are both low. wb is low whenever a byte is written by the am188er microcontroller. the byte write enables are driven in conjunction with the nonmultiplexed address bus as required for the write timing requirements of common srams. output enable the AM186ER and am188er microcontrollers provide the rd (read) signal which acts as an output enable. the rd signal is low when a word or byte is read by the AM186ER or am188er microcontroller. 42 am186 tm er and am188 tm er microcontrollers data sheet draft figure 4. am186?er microcontroller address busnormal operation figure 5. am186?er microcontrolleraddress bus disable in effect clkouta t 1 t 2 t 3 t 4 ad15Cad0 (read) data ad15Cad0 (write) lcs or ucs address data address address phase data phase a19Ca0 address mcs x, pcs x clkouta t 1 t 2 t 3 t 4 ad15Cad0 (write) data lcs or ucs ad15Cad8 (read) ad7Cad0 (read) address phase data data phase data a19Ca0 address am186 tm er and am188 tm er microcontrollers data sheet 43 draft figure 6. am188?er microcontroller address busnormal operation figure 7. am188?er microcontrolleraddress bus disable in effect clkouta t 1 t 2 t 3 t 4 ad7Cad0 (read) data ao15Cao8 (read or write) ad7Cad0 (write) address address data address address phase data phase a19Ca0 address lcs or ucs mcs x, pcs x clkouta t 1 t 2 t 3 t 4 ad7Cad0 (read) data address ao15Cao8 lcs or ucs ad7Cad0 (write) data address phase data phase a19Ca0 address 44 am186 tm er and am188 tm er microcontrollers data sheet draft pseudo static ram (psram) support the AM186ER and am188er microcontrollers support the use of psram devices in low memory chip-select (lcs) space only. when psram mode is enabled, the timing for the lcs signal is modified by the chip-select control unit to provide a cs precharge period during psram accesses. the 50-mhz timing of the AM186ER and am188er microcontrollers is appropri- ate to allow 70-ns psram to run with one wait state. psram mode is enabled through a bit in the low mem- ory chip-select (lmcs) register. the psram feature is disabled on cpu reset. in addition to the lcs timing changes for psram pre- charge, the psram devices also require periodic re- fresh of all internal row addresses to retain their data. although refresh of psram can be accomplished sev- eral ways, the AM186ER and am188er microcontrol- lers implement auto refresh only. the AM186ER and am188er microcontrollers gener- ate rfsh , a refresh signal, to the psram devices when psram mode is enabled. no refresh address is required by the psram when using the auto refresh mechanism. the rfsh signal is multiplexed with the mcs 3 signal pin. when psram mode is enabled, mcs 3 is not available for use as a chip-select signal. the refresh control unit must be programmed before accessing psram in lcs space. the refresh counter in the clock prescaler (cdram) register must be con- figured with the required refresh interval value. the re- fresh counter reload value in the cdram register should not be set to less than 18 (12h) in order to pro- vide time for processor cycles between refreshes. the refresh address counter must be set to 000000h to pre- vent the mcs 3Cmcs 0 or pcs 6Cpcs 0 chip selects from asserting. ucs may randomly assert during a psram refresh. lcs is held high and the a bus is not used during re- fresh cycles. the lmcs register must be configured to external ready ignored (r2 = 1) with one wait state (r1Cr0 = 01b), and the psram mode enable bit (se) must be set. the ending address of lcs space in the lmcs register must also be programmed. peripheral control block (pcb) the integrated peripherals of the AM186ER and am188er microcontrollers are controlled by 16-bit read/write registers. the peripheral registers are con- tained within an internal 256-byte control block. the registers are physically located in the peripheral de- vices they control, but they are addressed as a single 256-byte block. figure 9 on page 46 shows a map of these registers. reading and writing the pcb code intended to execute on the am188er microcon- troller should perform all writes to the pcb registers as byte writes. these writes will transfer 16 bits of data to the pcb register even if an 8-bit register is named in the instruction. for example, out dx, al results in the ax value being written to the port address in dx . reads to the pcb should be done as word reads. code written in this manner will run correctly on the am188er and AM186ER microcontrollers. unaligned reads and writes to the pcb result in unpre- dictable behavior on both the AM186ER and am188er microcontrollers. for a complete description of all the registers in the pcb, refer to the AM186ER and am188er microcon- trollers users manual , order #21684. clock and power management the clock and power management unit of the AM186ER and am188er microcontrollers includes a phase-locked loop (pll) and a second programmable system clock output (clkoutb). phase-locked loop (pll) in a traditional 80c186/80c188 design, the internal clock frequency is half the frequency of the crystal. because of the internal pll on the AM186ER and am188er micro- controllers, the internal clock generated by both micro- controllers can operate at up to four times the frequency of the crystal. the AM186ER and am188er microcon- trollers operate in the following modes: n divide by twofrequency of the system clock is half the frequency of the crystal with pll disabled. n times onefrequency of the system clock will be the same as the external crystal with pll enabled. n times fourfrequency of the system clock is four times the frequency of the crystal with pll enabled. the default times four mode must be used for processor frequencies above 40 mhz. the divide by two mode should be used for frequencies below 16 mhz. the clock- ing mode is selected using clksel 1 and clksel 2 on reset. table 8 provides the maximum and minimum fre- quencies for x1, x2, and clkouta according to clocking mode. table 8. maximum and minimum clock frequencies mode x1/x2 max x1/x2 min clkouta max clkouta min divide by 2 40 mhz 30 mhz 20 mhz 15 mhz times 1 40 mhz 16 mhz 40 mhz 16 mhz times 4 12.5 mhz 4 mhz 50 mhz 16 mhz am186 tm er and am188 tm er microcontrollers data sheet 45 draft crystal-driven clock source the internal oscillator circuit of the AM186ER and am188er microcontrollers is designed to function with a parallel-resonant fundamental mode crystal. be- cause of the pll, the crystal frequency can be twice, equal to, or one quarter of the processor frequency. do not replace a crystal with an lc or rc equivalent. see figure 8 for a diagram of oscillator configurations. the x1 and x2 signals are connected to an internal in- verting amplifier (oscillator) that provides, along with the external feedback loading, the necessary phase shift. in such a positive feedback circuit, the inverting amplifier has an output signal (x2) 180 degrees out of phase of the input signal (x1). the external feedback network provides an additional 180-degree phase shift. in an ideal system, the input to x1 will have 360 or zero degrees of phase shift. the ex- ternal feedback network is designed to be as close to ideal as possible. if the feedback network is not provid- ing necessary phase shift, negative feedback will dampen the output of the amplifier and negatively af- fect the operation of the clock generator. values for the loading on x1 and x2 must be chosen to provide the necessary phase shift and crystal operation. selecting a crystal when selecting a crystal, the load capacitance should always be specified (c l ). this value can cause vari- ance in the oscillation frequency from the desired spec- ified value (resonance). the load capacitance and the loading of the feedback network have the following re- lationship: where c s is the stray capacitance of the circuit. placing the crystal and c l in series across the inverting ampli- fier and tuning these values (c 1 , c 2 ) allows the crystal to oscillate at resonance. finally, there is a relationship between c 1 and c 2 . to enhance the oscillation of the inverting amplifier, these values need to be offset with the larger load on the output (x2). equal values of these loads will tend to balance the poles of the invert- ing amplifier. the characteristics of the inverting amplifier set limits on the following parameters for crystals: esr (equivalent series resistance)60-ohm max drive level .......................... 500-mw max the recommended range of values for c 1 and c 2 are as follows: c 1 ........................................ 15 pf 20% c 2 ........................................ 22 pf 20% the specific values for c 1 and c 2 must be determined by the designer and are dependent on the characteris- tics of the chosen crystal and board design. external source clock alternately, the internal oscillator can be driven by an external clock source. the external clock source should be connected to the input of the inverting ampli- fier (x1) with the output (x2) left unconnected. x1 and x2 are not 5-v tolerant and x1 has a maximum input equal to v cc . figure 8. am186?er and am188?er microcontrollers oscillator configurations (c 1 c 2 ) c l = ( c 1 + c 2 ) + c s crystal x1 b. crystal configuration c 1 c 2 x2 to pll oscillator a. external clock configuration microcontroller am188er/ x1 x2 to pll oscillator AM186ER microcontroller am188er/ AM186ER notes: x1 and x2 are not 5-v tolerant. the x1 maximum input is v cc . 46 am186 tm er and am188 tm er microcontrollers data sheet draft figure 9. peripheral control block register map serial port status register serial port transmit register serial port receive register serial port baud rate divisor register pcs and mcs auxiliary register memory partition register pdcon register reset configuration register upper memory chip select register enable rcu register a8 da e0 f0 f6 peripheral control block relocation register fe register name ww ww ww ww ww changed from original am186 microcontroller f4 note : gaps in offset addresses indicate reserved registers. no access should be made to reserved registers. offset (hexadecimal) e2 e4 d8 d6 d4 d2 ca c8 c6 c4 c2 c0 clock prescaler register dma 1 control register dma 1 transfer count register dma 1 destination address low register dma 1 source address high register dma 1 source address low register dma 0 control register dma 0 transfer count register dma 0 destination address high register dma 0 destination address low register d0 dma 0 source address low register dma 0 source address high register a6 a4 a2 a0 midrange memory chip select register peripheral chip select register low memory chip select register 80 82 84 86 88 processor release level register dma 1 destination address high register serial port control register * changed from am186em and am188em microcontrollers * internal memory chip select register ac ** new to the AM186ER and am188er microcontrollers ** watchdog timer control register e6 ** am186 tm er and am188 tm er microcontrollers data sheet 47 draft figure 9. peripheral control block register map (continued) offset (hexadecimal) 10 12 14 16 18 3e 40 42 70 72 74 register name ww ww ww changed from original am186 microcontroller 44 76 78 7a notes : gaps in offset addresses indicate reserved registers. no access should be made to reserved registers. 5c 5e 60 62 66 50 52 54 56 58 5a timer 2 mode/control register timer 2 maxcount compare a register timer 2 count register timer 1 mode/control register timer 1 maxcount compare b register timer 1 maxcount compare a register timer 1 count register timer 0 mode/control register timer 0 maxcount compare b register timer 0 maxcount compare a register timer 0 count register 3c 3a 38 36 34 32 30 2e 2c 2a 28 26 24 22 20 pio data 1 register pio direction 1 register pio mode 0 register pio mode 1 register pio data 0 register pio direction 0 register int2 control register int1 control register int0 control register dma 1 interrupt control register dma 0 interrupt control register timer interrupt control register interrupt status register interrupt request register in-service register interrupt mask register poll status register poll register end-of-interrupt register interrupt vector register synchronous serial transmit 1 register int3 control register serial port interrupt control register watchdog timer interrupt control register int4 control register synchronous serial receive register synchronous serial transmit 0 register synchronous serial enable register synchronous serial status register priority mask register 48 am186 tm er and am188 tm er microcontrollers data sheet draft figure 10. clock organization system clocks the base system clock of the original am186/am188 microcontrollers is renamed clkouta and the addi- tional output is called clkoutb. clkouta and clk- outb operate at either the fundamental processor frequency or the cpu clock (power-save) frequency. figure 10 shows the organization of the clocks. the second clock output (clkoutb) allows one clock to run at the fundamental frequency and the other clock to run at the cpu (power-save) frequency. individual drive enable bits allow selective enabling of just one, or both, of these clock outputs. power-save operation the power-save mode of the AM186ER and am188er microcontrollers reduces power consump- tion and heat dissipation, thereby extending battery life in portable systems. in power-save mode, operation of the cpu and internal peripherals continues at a slower clock frequency. when a hardware interrupt occurs, the microcontroller automatically returns to its normal op- erating frequency. the microcontroller remains in power-save mode for software interrupts and traps. note: power-save operation requires that clock- dependent peripherals be reprogrammed for clock frequency changes. software drivers must be aware of clock frequency. initialization and processor reset processor initialization or startup is accomplished by driving the res input pin low. res must be held low for 1 ms during power-up to ensure proper device ini- tialization. res forces the AM186ER and am188er microcontrollers to terminate all execution and local bus activity. no instruction or bus activity occurs as long as res is active. after res becomes inactive and an internal processing interval elapses, the microcontrol- ler begins execution with the instruction at physical lo- cation ffff0h. res also sets some registers to predefined values. note that all clock selection (s6/ clksel 1 and uzi /clksel 2) must be stable four clocks prior to the deassertion of res . activating the pll will require 1 ms to achieve a stable clock. reset configuration register when the res input is asserted low, the contents of the address/data bus (ad15Cad0) are written into the reset configuration register. the system can place configuration information on the address/data bus using weak external pullup or pulldown resistors, or using an external driver that is enabled during reset. the processor does not drive the address/data bus during reset. for example, the reset configuration register could be used to provide the software with the position of a configuration switch in the system. using weak external pullup and pulldown resistors on the address and data bus, the system would provide the microcontroller with a value corresponding to the position of the jumper dur- ing a reset. the reset configuration register can only be modified during reset. this register is read-only during normal operation. power-save divisor 1 (/1 to /128) cbf 1 mux caf 1 mux psen 1 pll mux clkouta clkoutb x1, x2 cpu clock time delay 6 2.5ns ? 2 input clock clksel 2 clksel 1 cad 1 cbd 1 fundamental clock 1x or 4x mux notes: 1. set via pdcon register am186 tm er and am188 tm er microcontrollers data sheet 49 draft chip-select unit the AM186ER and am188er microcontrollers contain logic that provides programmable chip-select genera- tion for both memories and peripherals. the logic can be programmed to provide external ready and wait- state generation and latched address bits a1 and a2. the chip-select lines are active for all memory and i/o cycles in their programmed areas, whether they are generated by the cpu or by the integrated dma unit. chip-select timing the timing for the ucs and lcs outputs is modified from the original am186 microcontroller. these outputs now assert in conjunction with the nonmultiplexed ad- dress bus for normal memory timing. to enable these outputs to be available earlier in the bus cycle, the num- ber of programmable memory size selections has been reduced. ready and wait-state programming the AM186ER and am188er microcontrollers can be programmed to sense a ready signal for each of the ex- ternal peripheral or memory chip-select lines. the ex- ternal ready signal can be either the ardy or srdy signal as shown in figure 11. for diagrams of the syn- chronous ready waveforms and asynchronous ready waveforms, refer to page 97. each external chip-select control register (umcs, lmcs, mmcs, pacs, and mpcs) contains a single-bit field that determines whether the external ready signal is required or ig- nored. the internal memory ignores the external ready signal. the number of wait states to be inserted for each ac- cess to an external peripheral or memory region is pro- grammable. the chip-select control registers for ucs , lcs , mcs 3Cmcs 0, pcs 6, and pcs 5 contain a two-bit field that determines the number of wait states from zero to three to be inserted. pcs 3Cpcs 0 use three bits to provide additional values of 5, 7, 9, and 15 wait states. the chip-select control register for internal memory always specifies no wait states. when external ready is required, internally pro- grammed wait states will always complete before exter- nal ready can terminate or extend a bus cycle. for example, if the internal wait states are set to insert two wait states, the processor samples the external ready pin during the first wait cycle. if external ready is as- serted at that time, the access completes after six cy- cles (four cycles plus two wait states). if external ready is not asserted during the first wait state, the access is extended until ready is asserted, which is followed by one more wait state followed by t 4 . figure 11. ardy and srdy synchronization logic diagram d q rising edge d q falling edge dq falling edge bus ready srdy clkouta ardy 50 am186 tm er and am188 tm er microcontrollers data sheet draft memory maps there are several possible ways to configure the ad- dress space of the AM186ER and am188er microcon- trollers. four of the most popular configurations are shown in figure 12. figure 12. example memory maps external flash (ucs) internal ram 0 kbyte 32 kbytes 512 kbytes 1 mbyte 512 kbytes flash 256 kbytes flash no external ram external flash (ucs) internal ram 0 kbyte 32 kbytes 768 kbytes 1 mbyte external ram (mcs) internal ram at 0 32 kbytes external ram external flash (ucs) internal ram 0 kbyte 32 kbytes 512 kbytes 1 mbyte 512 kbytes flash 256 kbytes external ram 256 kbytes external ram (mcs3Cmcs0) internal ram at 0 external flash (ucs) 0 kbyte 768 kbytes 1 mbyte 512 kbytes external ram internal ram 544 kbytes (lcs) 256 kbytes flash 512 kbytes external ram internal ram located above external ram shaded areas represent open memory that can be used by other chip selects and the pcb, if located in memory. am186 tm er and am188 tm er microcontrollers data sheet 51 draft chip-select overlap although programming the various chip selects on the AM186ER microcontroller so that multiple chip select signals are asserted for the same physical address is not recommended, it may be unavoidable in some sys- tems. in such systems, the chip selects whose asser- tions overlap must have the same configuration for ready (external ready required or not required) and the number of wait states to be inserted into the cycle by the processor. the peripheral control block (pcb) and the internal memory are both accessed using internal signals. these internal signals function as chip selects config- ured with zero wait states and no external ready. there- fore, the pcb and internal memory can be programmed to addresses that overlap external chip select signals if those external chip selects are pro- grammed to zero wait states with no external ready re- quired. when overlapping an additional chip select with either the lcs or ucs chip selects, it must be noted that set- ting the disable address (da) bit in the lmcs or umcs register will disable the address from being driven on the ad bus for all accesses for which the associated chip select is asserted, including any accesses for which multiple chip selects assert. the mcs and pcs chip select pins can be configured as either chip selects (normal function) or as pio inputs or outputs. it should be noted; however, that the ready and wait state generation logic for these chip selects is in effect regardless of their configurations as chip se- lects or pios. this means that if these chip selects are enabled (by a write to the mmcs and mpcs for the mcs chip selects, or by a write to the pacs and mpcs registers for the pcs chip selects), the ready and wait state programming for these signals must agree with the programming for any other chip selects with which their assertion would overlap if they were configured as chip selects. although the pcs 4 signal is not available on an exter- nal pin, the ready and wait state logic for this signal still exists internal to the part. for this reason, the pcs 4 ad- dress space must follow the rules for overlapping chip selects. the ready and wait-state logic for pcs 6Cpcs 5 is disabled when these signals are configured as ad- dress bits a2Ca1. failure to configure overlapping chip selects with the same ready and wait state requirements may cause the processor to hang with the appearance of waiting for a ready signal. this behavior may occur even in a system in which ready is always asserted (ardy or srdy tied high). configuring pcs in i/o space with lcs or any other chip select configured for memory address 0 is not consid- ered overlapping of the chip selects. overlapping chip selects refers to configurations where more than one chip select asserts for the same physical address. upper memory chip select the AM186ER and am188er microcontrollers provide a ucs chip select for the top of memory. on reset, the AM186ER and am188er microcontrollers begin fetch- ing and executing instructions starting at memory loca- tion ffff0h. therefore, upper memory is usually used as instruction memory. to facilitate this usage, ucs de- faults to active on reset, with a default memory range of 64 kbyte from f0000h to fffffh, with external ready required and three wait states automatically inserted. the ucs memory range always ends at fffffh. the lower boundary is programmable. the upper memory chip select is configured through the upper memory chip select (umcs) register. during the address phase of a bus cycle when ucs is asserted, the da bit in the umcs register enables or disables the ad15Cad0 bus. if the da bit is set to 1, ad15Cad0 is not driven during the address phase of a bus cycle when ucs is asserted. if da is cleared to 0, ad15Cad0 is driven during the address phase of a bus cycle. disabling ad15Cad0 reduces power consump- tion and eliminates potential bus conflicts with memory or peripherals at high clock rates. the da bit in the umcs register defaults to 0 at power-on reset. low memory chip select the AM186ER and am188er microcontrollers provide an lcs chip select for the bottom of memory. because the interrupt vector table is located at the bottom of memory starting at 00000h, the lcs pin has tradition- ally been used to control data memory. the lcs pin is not active on reset. the AM186ER and am188er mi- crocontrollers also allow the imcs register and inter- nal memory to be programmed to address 0. this would allow the internal memory to be used for the in- terrupt vector table and data memory. midrange memory chip selects the AM186ER and am188er microcontrollers provide four chip selects, mcs 3Cmcs 0, for use in a user-locat- able memory block. the base address of the memory block can be located anywhere within the 1-mbyte memory address space, exclusive of the areas associ- ated with the ucs and lcs chip selects, as well as the address range of the peripheral chip selects, pcs 6, pcs 5, and pcs 3Cpcs 0, if they are mapped to mem- ory. the mcs address range can overlap the pcs ad- dress range if the pcs chip selects are mapped to i/o space. unlike the ucs and lcs chip selects, the mcs outputs assert with the multiplexed ad address bus. 52 am186 tm er and am188 tm er microcontrollers data sheet draft peripheral chip selects the AM186ER and am188er microcontrollers provide six chip selects, pcs 6Cpcs 5 and pcs 3Cpcs 0, for use within a user-locatable memory or i/o block. pcs 4 is not available on the AM186ER and am188er micro- controllers. the base address of the memory block can be located anywhere within the 1-mbyte memory ad- dress space, exclusive of the areas associated with the ucs , lcs , and mcs chip selects, or they can be con- figured to access the 64-kbyte i/o space. the pcs pins are not active on reset. pcs 6Cpcs 5 can have from zero to three wait states. pcs 3Cpcs 0 can have four additional wait-state values5, 7, 9, and 15. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. internal memory the AM186ER and am188er microcontrollers provide 32 kbyte of on-chip ram. the integration of memory helps to reduce the overall cost, power, and size of sys- tem designs. the internal memory also improves reli- ability with fewer connections and eases inventory management and system qualification because of the integrated supply. the internal ram for the AM186ER microcontroller is a 16k x 16-bit-wide array (32 kbyte) which provides the same performance as 16-bit external zero-wait-state ram. for the am188er microcontroller, the internal ram is a 32k x 8-bit-wide array (32 kbyte) that pro- vides the same performance as 8-bit external zero wait-state ram. interaction with external ram the AM186ER and am188er microcontrollers include an internal memory chip select (imcs) register to control the mapping of the internal ram. the internal address space can be located at any 32-kbyte bound- ary within the 1-mbyte memory address space, pro- vided that it does not overlap any external chip selects. if an overlap does occur, the external chip select must be set to 0 wait states and to ignore external ready. if the internal and external chip selects overlap, both will be active, but the internal memory data will be used on reads. writes, with all the corresponding external con- trol signals, will occur to both devices. special system consideration must be made for show read cycles, since those cycles will drive data out on reads. if internal and external chip selects overlap and the ex- ternal chip selects are not set to 0 wait states and to ig- nore external ready, the results are unpredictable. because of the many potential problems with overlap- ping chip selects, this practice is not recommended. the base address of the internal ram is determined by the value of bits ba19Cba15 in the imcs register. be- cause the interrupt vector table is located at 00000h, it is not unusual to store the interrupt vector table in the internal ram for faster access, and thus program the imcs register for a base address of 0. however, this scenario may lead to a memory address overlap be- tween the imcs and low memory chip select (lmcs) registers, as the base address of the lmcs register is always 0 if activated. emulator and debug modes there are two debug modes associated with the inter- nal memory. one mode allows users to disable the in- ternal ram, and the other mode makes it possible to drive data on the external data bus during internal ram read cycles. normal operation of internal ram has all control signals for reads and writes and data for writes visible externally. accesses to internal memory can be detected externally by comparing the address on a19Ca0 with the address space of the internal memory. internal memory disable when this mode is activated, the internal ram is dis- abled and all accesses into the internal memory space are made externally for debugging purposes. this mode is activated by pulling the s 1/imdis pin low dur- ing reset. to use this debug mode, internal memory space must first be activated via the imcs register. show read enable when this mode is activated, the data from the internal ram read cycles are driven on the ad15Cad0 bus. note that if a byte read is being shown, the unused byte will also be driven on the ad15Cad0 bus. this mode can be activated externally by pulling the s 0/sren pin low during reset or by setting the sr bit in the imcs register. if this feature is activated externally using the sren pin, the value of the sr bit is ignored. many em- ulators assert the sren pin. during an internal memory read with show read en- abled, the address will be driven on the ad bus during t 1 and t 2 . the data being read will be driven on the ad bus during t 3 and t 4 by the AM186ER or am188er mi- crocontrollers. special system care must be taken to avoid bus contention, because normal reads have the ad bus three-stated during t 2 , t 3 , and t 4 . it is best to en- sure that no external device overlaps the internal mem- ory space. am186 tm er and am188 tm er microcontrollers data sheet 53 draft refresh control unit the refresh control unit (rcu) automatically generates refresh bus cycles. after a programmable period of time, the rcu generates a memory read request to the bus in- terface unit. if the address generated during a refresh bus cycle is within the range of a properly programmed chip select, that chip select (with the exception of ucs and lcs ) is activated when the bus interface unit executes the refresh bus cycle. the ready logic and wait states pro- grammed for the region are also in force. if no chip select is activated, then external ready is required to terminate the refresh bus cycle. if the hlda pin is active when a refresh request is gen- erated (indicating a bus hold condition), then the AM186ER and am188er microcontrollers deactivate the hlda pin in order to perform a refresh cycle. the external bus master must remove the hold signal for at least one clock in order to allow the refresh cycle to execute. the sequence of hlda going inactive while hold is being held active can be used to signal a pending refresh request. the AM186ER and am188er microcontrollers hold latency time, the period between hold request and hold acknowledge, is a function of the activity occur- ring in the processor when the hold request is re- ceived. a hold request is second only to dram refresh requests in priority of activity requests received by the processor. for example, in the case of a dma transfer, the hold latency can be as great as four bus cycles. this occurs if a dma word transfer operation is taking place from an odd address to an odd address (AM186ER microcontroller only). this is a total of 16 or more clock cycles if wait states are required. in addition, if locked transfers are performed, the hold latency time is increased by the length of the locked transfer. interrupt control unit the AM186ER and am188er microcontrollers can re- ceive interrupt requests from a variety of sources, both internal and external. the internal interrupt controller arranges these requests by priority and presents them one at a time to the cpu. there are six external interrupt sources on the AM186ER/am188er microcontrollersfive maskable interrupt pins and one nonmaskable interrupt pin. in ad- dition, there are six total internal interrupt sources three timers, two dma channels, and the asynchronous serial portthat are not connected to external pins. the AM186ER and am188er microcontrollers provide three interrupt sources not present on the am186 and am188 microcontrollers. the first is an additional exter- nal interrupt pin (int4), which operates much like the already existing interrupt pins (int3Cint0). the sec- ond is an internal maskable watchdog timer interrupt. the third is an internal interrupt from the asynchronous serial port. the five maskable interrupt request pins can be used as direct interrupt requests. plus, int3Cint0 can be cascaded with an 82c59a-compatible external inter- rupt controller if more inputs are needed. an external interrupt controller can be used as the system master by programming the internal interrupt controller to op- erate in slave mode. in all cases, nesting can be en- abled so that service routines for lower priority interrupts are interrupted by a higher priority interrupt. programming the interrupt control unit the AM186ER and am188er microcontrollers provide two methods for masking and unmasking the maskable interrupt sources. each interrupt source has an inter- rupt control register (offsets 32hC44h) that contains a mask bit specific to that interrupt. in addition, the inter- rupt mask register (offset 28h) is provided as a single source to access all of the mask bits. while changing a mask bit in either the mask register or the individual register will change the corresponding mask bit in the other register, there is a difference in exactly how the mask is updated. if the interrupt mask register is written while interrupts are enabled, it is possible that an interrupt could occur while the register is in an undefined state. this can cause interrupts to be accepted even though they were masked both before and after the write to the interrupt mask register. therefore, the interrupt mask register should only be written when interrupts are disabled. mask bits in the individual interrupt control registers can be written while interrupts are enabled, and there will be no erroneous interrupt operation. timer control unit there are three 16-bit programmable timers in the AM186ER and am188er microcontrollers. timer 0 and timer 1 are connected to four external pins (each has an input and an output). these two timers can be used to count, time external events, or generate nonrepetitive or variable-duty-cycle waveforms. in addition, timer 1 can be configured as a watchdog timer interrupt. note that a hardware watchdog timer (wdt) has been added to the AM186ER and am188er microcontrollers. use of the wdt is recommended for applications requir- ing this reset functionality. to maintain compatibility with previous versions of the AM186ER and am188er mi- crocontrollers, timer 1 can be configured as a watchdog timer and can generate a maskable watchdog timer in- terrupt. the maskable watchdog timer interrupt provides a mechanism for detecting software crashes or hangs. the tmrout1 output is internally connected to the watchdog timer interrupt. the timer1 count register must then be reloaded at intervals less than the timer1 max count to assure the watchdog interrupt is not taken. 54 am186 tm er and am188 tm er microcontrollers data sheet draft if the code crashes or hangs, the timer1 countdown will cause a watchdog interrupt. timer 2 is not connected to any external pins. it can be used for real-time coding and time-delay applications. it can also be used as a prescale to timers 0 and 1, or as a dma request source. the timers are controlled by eleven 16-bit registers in the peripheral control block. a timers timer-count reg- ister contains the current value of that timer. the timer- count register can be read or written with a value at any time, whether the timer is running or not. the microcon- troller increments the value of the timer-count register each time a timer event occurs. each timer also has a maximum-count register that de- fines the maximum value the timer will reach. when the timer reaches the maximum value, it resets to 0 during the same clock cyclethe value in the maximum-count register is never stored in the timer-count register. also, timers 0 and 1 have a secondary maximum-count reg- ister. using both the primary and secondary maximum- count registers lets the timer alternate between two maximum values. if the timer is programmed to use only the primary max- imum-count register, the timer output pin switches low for one clock cycle after the maximum value is reached. if the timer is programmed to use both of its maximum- count registers, the output pin indicates which maxi- mum-count register is currently in control, thereby cre- ating a waveform. the duty cycle of the waveform depends on the values in the maximum-count regis- ters. each timer is serviced every fourth clock cycle, so a timer can operate at a speed of up to one-quarter the internal clock frequency. a timer can be clocked exter- nally at this same frequency; however, because of in- ternal synchronization and pipelining of the timer circuitry, the timer output may take up to six clock cy- cles to respond to the clock or gate input. watchdog timer the AM186ER/am188er microcontrollers provide a hardware watchdog timer. the watchdog timer (wdt) can be used to regain control of the system when soft- ware fails to respond as expected. the wdt is inactive after reset. it can be modified only once by a keyed se- quence of writes to the watchdog timer control regis- ter (wdtcon) following reset. this single write can either disable the timer or modify the timeout period and the action taken upon timeout. a keyed sequence is also required to reset the current wdt count. this behavior ensures that randomly executing code will not prevent a wdt event from occurring. the wdt supports up to a 1.34-second timeout period in a 50-mhz system. the wdt can be configured to cause either an nmi in- terrupt or a system reset upon timeout. if the wdt is configured for nmi, the nmiflag in the wdtcon register is set when the nmi is generated. the nmi in- terrupt service routine (isr) should examine this flag to determine if the interrupt was generated by the wdt or by an external source. if the nmiflag is set, the isr should clear the flag by writing the correct keyed se- quence to the wdtcon register. if the nmiflag is set when a second wdt timeout occurs, a wdt sys- tem reset is generated rather than a second nmi event. when the processor takes a wdt reset, either be- cause of a single wdt event with the wdt configured to generate resets or due to a wdt event with the nmi- flag set, the rstflag in the wdtcon register is set. this allows system initialization code to differenti- ate between a hardware reset and a wdt reset and take appropriate action. the rstflag is cleared when the wdtcon register is read or written. the processor does not resample external pins during a wdt reset. this means that the clocking, the reset configuration register, and any other features that are user-selectable during reset do not change when a wdt system reset occurs. pio mode and pio direc- tion registers are not affected and pio data is unde- fined. all other activities are identical to those of a normal system reset. note: the watchdog timer (wdt) is inactive after reset. direct memory access direct memory access (dma) permits transfer of data between memory and peripherals without cpu involve- ment. the dma unit in the AM186ER and am188er microcontrollers, shown in figure 13, provides two high-speed dma channels. data transfers can occur between memory and i/o spaces (e.g., memory to i/o) or within the same space (e.g., memory-to-memory or i/o-to-i/o). additionally, bytes (also words on the AM186ER microcontroller) can be transferred to or from even or odd addresses. only two bus cycles (a minimum of eight clocks) are necessary for each data transfer. each channel accepts a dma request from one of the four sources: the channel request pin (drq1Cdrq0), timer 2, a serial port, or system software. the two dma channels can be programmed with different prior- ities to resolve simultaneous dma requests, and trans- fers on one channel can interrupt the other channel. the dma channels can be directly connected to the asynchronous serial port. dma and serial port transfer is accomplished by programming the dma controller to perform transfers between a data source in memory or i/o space and a serial port transmit or receive register. am186 tm er and am188 tm er microcontrollers data sheet 55 draft dma operation each channel has six registers in the peripheral control block that define specific channel operations. the dma registers consist of a 20-bit source address (two regis- ters), a 20-bit destination address (two registers), a 16- bit transfer count register, and a 16-bit control register. the dma transfer count register (dtc) specifies the number of dma transfers to be performed. up to 64k transfers can be performed with automatic termination. the dma control registers define the channel opera- tion. all registers can be modified during any dma ac- tivity. any changes made to the dma registers are reflected immediately in dma operation. the am188er microcontrollers maximum dma trans- fer rates are half that of those listed in table 9 for the AM186ER microcontroller. table 9. AM186ER microcontroller maximum dma transfer rates asynchronous serial port/dma transfers the enhanced AM186ER/am188er microcontrollers can dma to and from the asynchronous serial port. this is accomplished by programming the dma con- troller to perform transfers between a data buffer (lo- cated either in memory or i/o space) and an asynchronous serial port data register (sptd or sprd). note that when a dma channel is in use by the asynchronous serial port, the corresponding external dma request signal is deactivated. for dma to the asynchronous serial port, the transmit data register address, either i/o-mapped or memory- mapped, should be specified as a byte destination for the dma by writing the address of the register into the dma destination low and dma destination high regis- ters. the destination address (the address of the trans- mit data register) should be configured as a constant throughout the dma operation. the asynchronous se- rial port transmitter acts as the synchronizing device; therefore, the dma channel should be configured as destination-synchronized. for dma from the asynchronous serial port, the re- ceive data register address, either i/o-mapped or memory-mapped, should be specified as a byte source for the dma by writing the address of the register into the dma source and dma source high registers. the source address (the address of the receive data regis- ter) should be configured as a constant throughout the dma. the asynchronous serial port receiver acts as the synchronizing device; therefore, the dma channel should be configured as source- synchronized. dma channel control registers each dma control register determines the mode of op- eration for the particular dma channel. this register specifies the following: n mode of synchronization n whether bytes or words are transferred (AM186ER microcontroller only) n whether an interrupt is generated after the last transfer n whether dma activity ceases after a programmed number of dma cycles n relative priority of the dma channel with respect to the other dma channel n whether the source address is incremented, decre- mented, or maintained constant after each transfer n whether the source address addresses memory or i/o space n whether the destination address is incremented, decremented, or maintained constant after trans- fers n whether the destination address addresses mem- ory or i/o space dma priority the dma channels can be programmed so that one channel is always given priority over the other, or they can be programmed to alternate cycles when both have dma requests pending. dma cycles always have priority over internal cpu cycles, except between locked memory accesses or word accesses to odd memory locations. however, an external bus hold takes priority over an internal dma cycle. because an interrupt request, other than an nmi, can- not suspend a dma operation and the cpu cannot ac- cess memory during a dma cycle, interrupt latency time suffers during sequences of continuous dma cy- cles. an nmi request, however, causes all internal dma activity to halt. this allows the cpu to respond quickly to the nmi request. synchronization type maximum dma transfer rate (mbyte/s) 50 mhz 40 mhz 33 mhz 25 mhz unsynchronized 12.5 10 8.25 6.25 source synch 12.5 10 8.25 6.25 destination synch (cpu needs bus) 8.33 6.6 5.5 4.16 destination synch (cpu does not need bus) 10.00 8 6.6 5 56 am186 tm er and am188 tm er microcontrollers data sheet draft figure 13. dma unit block diagram asynchronous serial port the AM186ER and am188er microcontrollers provide an asynchronous serial port. the asynchronous serial port is a two-pin interface that permits full-duplex bidi- rectional data transfer. the asynchronous serial port supports the following features: n full-duplex operation n 7-bit or 8-bit data transfers n odd, even, or no parity n 1 or 2 stop bits if additional rs-232 signals are required, they can be created with available pio pins. the asynchronous se- rial port transmit and receive sections are double buff- ered. break character, framing, parity, and overrun error detection are provided. exception interrupt gener- ation is programmable by the user. the transmit/receive clock is based on the internal pro- cessor clock, which is divided down internally to the se- rial port operating frequency. the serial port permits 7- bit and 8-bit data transfers. dma transfers using the se- rial port are supported. the serial port generates one interrupt for any of three serial port eventstransmit complete, data received, and receive error. the serial port can be used in power-save mode, but the software must adjust the transfer rate to correctly reflect the new internal operating frequency and must ensure that the serial port does not receive any infor- mation while the frequency is being changed. dma transfers through the serial port the dma channels can be directly connected to the asynchronous serial port. dma and serial port transfer is accomplished by programming the dma controller to perform transfers between a memory or i/o space and a serial port transmit or receive register. for more infor- mation see the dma control register descriptions in the AM186ER and am188er microcontrollers users man- ual , order #21684. synchronous serial interface the synchronous serial interface (ssi) enables the AM186ER and am188er microcontrollers to communi- cate with application-specific integrated circuits (asics) that require reprogrammability but are short on pins. this four-pin interface permits half-duplex, bidirectional data transfer at speeds of up to 25 mbit/s. unlike the asynchronous serial port, the ssi operates in a master/slave configuration. the AM186ER and am188er microcontrollers are the master ports. the ssi interface provides four pins for communicating with system components: two enables (sden0 and sden1), a clock (sclk), and a data pin (sdata). five 20-bit adder/subtractor dma control logic request selection logic adder control logic 20 20 channel control register 1 channel control register 0 16 drq1/serial port drq0/serial port timer request interrupt request transfer counter ch. 1 destination address ch. 1 destination address ch. 0 transfer counter ch. 0 source address ch. 1 source address ch. 0 internal address/data bus am186 tm er and am188 tm er microcontrollers data sheet 57 draft registers are used to control and monitor the interface. refer to figure 14 and figure 15 on page 58 for dia- grams of ssi reads and writes. four-pin interface the two enable pins sden1Csden0 can be used di- rectly as enables for up to two peripheral devices. transmit and receive operations are synchronized be- tween the master (AM186ER or am188er microcon- troller) and slave (peripherals) by means of the sclk output. sclk is derived from the internal processor clock and is the processor clock divided by 2, 4, 8, or 16. programmable i/o (pio) pins there are 32 pins on the AM186ER and am188er mi- crocontrollers that are available as multipurpose sig- nals. table 3 and table 4 on page 36 list the pio pins. each of these pins can be used as a user-programma- ble input or output signal if the normal shared function is not needed. if a pin is enabled to function as a pio signal, the pre- assigned signal function is disabled and does not affect the level on the pin. a pio signal can be configured to operate as an input (with or without a weak pullup or pulldown), as an output, or as an open-drain output. configuration as an open-drain output is accomplished by keeping the appropriate pdata bits constant in the pio data register and writing the data value into its as- sociated bit position in the pio direction register, so the output is either driving low or is disabled, depending on the data. after power-on reset, the pio pins default to various configurations. the column titled power-on reset sta- tus in table 3 and table 4 on page 36 lists the defaults for the pios. the system initialization code must recon- figure the pios as required. note: wdt reset does not reset pio registers. the a19Ca17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address ffff0h. the dt/r , den , and srdy pins also default to normal operation on power-on reset. note that emulators use a19, a18, a17, s6, and uzi . system designers using these signals as pios should check with their emulator vendor for limitations on em- ulator operation. if the ad15Cad0 bus override is enabled on power-on reset, then s6 / clksel 2 and uzi / clksel 1 revert to normal operation instead of pio input with pullup. many emulators assert the aden override. if bhe /aden (AM186ER microcontroller) or rfsh 2/aden (am188er microcontroller) is held low during power- on reset, the ad15Cad0 bus override is enabled. 58 am186 tm er and am188 tm er microcontrollers data sheet draft figure 14. synchronous serial interface multiple write figure 15. synchronous serial interface multiple read sclk sden1 or sden0 sdata write to ssc, bit de=1 write to ssd poll sss for pb=0 write to ssd poll sss for pb=0 write to ssd write to ssc, bit de=0 poll sss for pb=0 pb=0 dr/dt=0 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=0 dr/dt=0 sclk sden1 or sden0 sdata write to ssc, bit de=1 write to ssd poll sss for pb=0 read from ssr (dummy) poll sss for pb=0 read from ssr write to ssc, bit de=0 poll sss for pb=0 pb=0 dr/dt=0 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=0 dr/dt=0 read from ssr am186 tm er and am188 tm er microcontrollers data sheet 59 draft low-voltage operation the low-voltage operation of the AM186ER and am188er microcontrollers is an enabling technology for the design of portable systems with long battery life. this capability, combined with cpu clock management, enables design of very low-power computing systems. low-voltage standard industry standards for low-voltage operation are emerging to facilitate the design of components that will make up a complete low-voltage system. as a guideline, the AM186ER and am188er microcontrol- ler specifications follow the first article or regulated ver- sion of the jedec 8.0 low-voltage proposal. this standard proposal calls for a v cc range of 3.3 v 10%. power savings cmos dynamic power consumption is proportional to the square of the operating voltage multiplied by capac- itance and operating frequency. static cpu operation can reduce power consumption by enabling the system designer to reduce operating frequency when possible. however, operating voltage is always the dominant fac- tor in power consumption. by reducing the operating voltage from 5 v to 3.3 v for any device, the power consumed is reduced by 56%. reduction of cpu and core logic operating voltage dra- matically reduces overall system power consumption. additional power savings can be realized as low-voltage mass storage and peripheral devices become available. two basic strategies exist in designing systems con- taining the AM186ER and am188er microcontrollers. the first strategy is to design a homogenous system in which all logic components operate at 3.3 v. this pro- vides the lowest overall power consumption. however, system designers may need to include devices for which 3.3-v versions are not available. in the second strategy, the system designer must then design a mixed 5-v/3.3-v system. this compromise enables the system designer to minimize the core logic power con- sumption while still including functionality of the 5-v features. the choice of a mixed voltage system design also involves balancing design complexity with the need for the additional features. input/output circuitry to accommodate current 5-v systems, the AM186ER and am188er microcontrollers have 5-v tolerant i/o drivers. the drivers produce ttl-compatible drive out- put (minimum 2.4-v logic high) and receive ttl and cmos levels (up to v cc + 2.6 v). the following are some design issues that should be considered when upgrading an AM186ER microcontroller 5-v design: n during power-up, if the 3.3-v supply has a signifi- cant delay in achieving stable operation relative to 5-v supply, then the 5-v circuitry in the system may start driving the processors inputs above the maxi- mum levels (v cc + 2.6 v). the system design should ensure that the 5-v supply does not exceed 2.6 v above the 3.3-v supply during a power-on se- quence. n preferably, all inputs will be driven by sources that can be three-stated during a system reset condition. the system reset condition should persist until sta- ble v cc conditions are met. this should help ensure that the maximum input levels are not exceeded during power-up conditions. n preferably, all pullup resistors will be tied to the 3.3-v supply, which will ensure that inputs requiring pullups are not over stressed during power-up. 60 am186 tm er and am188 tm er microcontrollers data sheet draft absolute maximum ratings temperature under bias: commercial (t c ) ........................0 c to + 100 c storage temperature .................. C65 c to + 125 c voltage on any pin with respect to ground.......................... C0.5 v to v cc + 2.6 v * notes: stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliability. * x1 and x2 are not 5-v-tolerant and have a range of C0 .5 v to v cc . operating ranges t c (commercial) ............................ 0 c to +100 c industrial * (t a ) .............................. C40 c to + 85 c v cc up to 50 mhz ............................. 3.3 v 0.3 v where: t c = case temperature t a = ambient temperature notes: operating ranges define those limits between which the functionality of the device is guaranteed. * industrial versions of AM186ER and am188er microcon- trollers are available in 25- and 33-mhz operating frequen- cies only. dc characteristics over commercial and industrial operating ranges notes: 1. this parameter is for inputs without pullup or pulldown resistors and for which 0 v in v cc . 2. this parameter is for inputs without pullup or pulldown resistors and for which 0 v in 5 v. 3. this parameter is for inputs with pulldown resistors and for which v ih = 2.4 v. 4. this parameter is for inputs with pullup resistors and for which v il = 0.45 v. 5. this parameter is for three-state outputs where v ext is driven on the three-state output and 0 v ext v cc . 6. this parameter is for three-state outputs where v ext is driven on the three-state output and 0 v ext 5 v . 7. this parameter has not been fully tested. 8. current is measured with the device in reset with x1 and x2 driven and all other non-power pins open but held high or low. preliminary symbol parameter description notes min max unit v il input low voltage C0.3 0.8 v v ih input high voltage 2.0 v cc + 2.6 v v ih clock input high voltage (x2, x1) v cc v v ol output low voltage i ol = 4.0 ma 0.45 v v oh output high voltage i oh = C1.0 ma 2.4 v i cc power supply current note 8 5.0 ma/ mhz i li input leakage current note 1 note 2 15 50 m a i ih input leakage current note 3 200 m a i il input leakage current note 4 C400 m a i lo output leakage current note 5 note 6 15 50 m a c in input capacitance f c =1 mhz (note 7) 10 pf c out i/o capacitance f c =1 mhz (note 7) 14 pf am186 tm er and am188 tm er microcontrollers data sheet 61 draft thermal characteristics tqfp package the AM186ER and am188er microcontrollers are specified for operation with case temperature ranges from 0 c to +100 c for a commercial temperature device. case temperature is measured at the top center of the package as shown in figure 16. the various temperatures and thermal resistances can be determined using the equations in figure 17 with information given in table 10. q ja is the sum of q jc and q ca . q jc is the internal thermal resistance of the assembly. q ca is the case to ambient thermal resistance. the variable p is power in watts. typical power supply current (i cc ) for the AM186ER and am188er microcontrollers is 3.7 ma per mhz of clock frequency. figure 16. thermal resistance ( c/watt) figure 17. thermal characteristics equations table 10. thermal characteristics ( c/watt) q ja q ca q jc q ja = q jc + q ca t c package/board airflow (linear feet per minute) q jc q ca q ja pqfp/2-layer 0 fpm 7 38 45 200 fpm 7 32 39 400 fpm 7 28 35 600 fpm 7 26 33 tqfp/2-layer 0 fpm 10 46 56 200 fpm 10 36 46 400 fpm 10 30 40 600 fpm 10 28 38 pqfp/4-layer to 6-layer 0 fpm 5 18 23 200 fpm 5 16 21 400 fpm 5 14 19 600 fpm 5 12 17 tqfp/4-layer to 6-layer 0 fpm 6 24 30 200 fpm 6 22 28 400 fpm 6 20 26 600 fpm 6 18 24 q ja = q jc + q ca p = i cc freq (mhz) v cc t j = t c + (p q jc ) t j = t a + (p q ja ) t c = t j C (p q jc ) t c = t a + (p q ca ) t a = t j C (p q ja ) t a = t c C (p q ca ) 62 am186 tm er and am188 tm er microcontrollers data sheet draft typical ambient temperatures the typical ambient temperature specifications are based on the following assumptions and calculations: the commercial operating range of the AM186ER and am188er microcontrollers is a case temperature t c of 0 to 100 degrees centigrade. t c is measured at the top center of the package. an increase in the ambient temperature causes a proportional increase in t c . the 50-mhz microcontroller is specified as 3.3 v, plus or minus 10%. therefore, 3.6 v is used for calculating typical power consumption on the 50-mhz microcontroller. typical power supply current (i cc ) in normal usage is estimated at 3.7 ma per mhz of microcontroller clock rate. typical power consumption can be calculated using the following formula: (watts) = (3.7 ma/mhz) 50 mhz (3.6 v/1000) table 11 shows the variables that are used to calculate the typical power consumption value for each version of the AM186ER and am188er microcontrollers. table 11. typical power consumption calculation thermal resistance is a measure of the ability of a package to remove heat from a semiconductor device. a safe operating range for the device can be calculated using the following formulas from figure 17 and the variables in table 10. by using the maximum case rating t c , the typical power consumption value from table 11, and q jc from table 10, the junction temperature t j can be calculated by using the following formula from figure 17. t j = t c + (p q jc ) table 12 shows t j values for the various versions of the AM186ER and am188er microcontrollers. the speed/pkg/board column in table 12 indicates the clock speed in mhz, the type of package (p for pqfp and t for tqfp), and the type of board (2 for 2-layer and 4C6 for 4-layer to 6-layer). table 12. junction temperature calculation by using t j from table 12, the typical power consumption value from table 11, and a q ja value from table 10, the typical ambient temperature t a can be calculated using the following formula from figure 17. t a = t j C (p q ja ) for example, t a for a 50-mhz pqfp design with a 2-layer board and 0 fpm airflow is calculated as follows: t a = 104.6 C (0.662 45) t a = 74.81 in this calculation, t j comes from table 12, p comes from table 11, and q ja comes from table 10. see table 13. t a for a 33-mhz tqfp design with a 4-layer to 6-layer board and 200 fpm airflow is calculated as follows: t a = 102.6 C (0.432 28) t a = 90.5 see table 16 for the result of this calculation. table 13 through table 16 and figure 18 through figure 21 show t a based on the preceding assumptions and calculations for a range of q ja values with airflow from 0 linear feet per minute to 600 linear feet per minute. p = mhz i cc volts / 1000 typical power (p) in watts mhz typical i cc volts 50 3.7 3.6 0.662 40 3.7 3.6 0.522 33 3.7 3.6 0.432 25 3.7 3.6 0.342 speed/ pkg/ board t j = t c + (p q jc ) t j t c p q jc 50/p2 100 0.662 7 104.6 50/t2 100 0.662 10 106.6 50/p4C6 100 0.662 5 103.3 50/t4C6 100 0.662 6 104.0 40/p2 100 0.522 7 103.7 40/t2 100 0.522 10 105.2 40/p4C6 100 0.522 5 102.6 40/t4C6 100 0.522 6 103.1 33/p2 100 0.432 7 103.0 33/t2 100 0.432 10 104.3 33/p4C6 100 0.432 5 102.2 33/t4C6 100 0.432 6 102.6 25/p2 100 0.342 7 102.4 25/t2 100 0.342 10 103.4 25/p4C6 100 0.342 5 101.7 25/t4C6 100 0.342 6 102.1 am186 tm er and am188 tm er microcontrollers data sheet 63 draft table 13 shows typical maximum ambient temperatures in degrees centigrade for a pqfp package used with a 2-layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case temperature. figure 18 illustrates the typical temperatures in table 13. table 13. typical ambient temperatures for pqfp with two-layer board figure 18. typical ambient temperatures for pqfp with two-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 50 mhz 0.662 74.81 78.8 81.43 82.8 40 mhz 0.522 80.2 83.3 85.4 86.5 33 mhz 0.432 83.56 86.2 87.9 88.7 25 mhz 0.342 87.0 89.1 90.4 91.1 airflow (linear feet per minute) 0 fpm 200 fpm 400 fpm 600 fpm typical ambient temperature (degrees c) n 50 mhz u 25 mhz u 33 mhz l 40 mhz legend: 74 78 82 86 90 94 l l l l v v v v u u u u n n n n 76 80 84 88 92 64 am186 tm er and am188 tm er microcontrollers data sheet draft table 14 shows typical maximum ambient temperatures in degrees centigrade for a tqfp package used with a 2-layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case temperature. figure 19 illustrates the typical temperatures in table 14. table 14. typical ambient temperatures for tqfp with two-layer board figure 19. typical ambient temperatures for tqfp with two-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 50 mhz 0.662 69.5 76.1 80.1 81.4 40 mhz 0.522 76.0 81.2 84.3 85.4 33 mhz 0.432 80.1 84.4 87.0 87.9 25 mhz 0.342 84.2 87.7 89.7 90.4 airflow (linear feet per minute) 0 fpm 200 fpm 400 fpm 600 fpm typical ambient temperature (degrees c) n 50 mhz u 25 mhz u 33 mhz l 40 mhz legend: 70 75 80 85 90 95 l l l l v v v v u u u u n n n n 65 am186 tm er and am188 tm er microcontrollers data sheet 65 draft table 15 shows typical maximum ambient temperatures in degrees centigrade for a pqfp package used with a 4-layer to 6-layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case temperature. figure 20 illustrates the typical temperatures in table 15. table 15. typical ambient temperatures for pqfp with four-layer to six-layer board figure 20. typical ambient temperatures for pqfp with four-layer to six-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 50 mhz 0.662 88.0 89.4 90.7 92.0 40 mhz 0.522 90.6 91.6 92.7 93.7 33 mhz 0.432 92.3 93.1 93.9 94.9 25 mhz 0.342 93.8 94.5 95.2 95.9 airflow (linear feet per minute) 0 fpm 200 fpm 400 fpm 600 fpm typical ambient temperature (degrees c) n 50 mhz u 25 mhz u 33 mhz l 40 mhz legend: 87 89 91 93 95 97 l l l l v v v v u u u u n n n n 88 90 92 94 96 66 am186 tm er and am188 tm er microcontrollers data sheet draft table 16 shows typical maximum ambient temperatures in degrees centigrade for a tqfp package used with a 4-layer to 6-layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case temperature. figure 21 illustrates the typical temperatures in table 16. table 16. typical ambient temperatures for tqfp with four-layer to six-layer board figure 21. typical ambient temperatures for tqfp with four-layer to six-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 50 mhz 0.662 84.1 85.5 86.8 88.1 40 mhz 0.522 87.44 88.5 89.5 90.6 33 mhz 0.432 89.64 90.5 91.4 92.2 25 mhz 0.342 91.84 92.5 93.2 93.9 airflow (linear feet per minute) 0 fpm 200 fpm 400 fpm 600 fpm typical ambient temperature (degrees c) n 50 mhz u 25 mhz u 33 mhz l 40 mhz legend: 87 89 91 93 95 97 l l l l v v v v u u u u n n n n 88 90 92 94 96 86 85 84 am186 tm er and am188 tm er microcontrollers data sheet 67 draft commercial and industrial switching characteristics and waveforms in the switching waveforms that follow, several abbreviations are used to indicate the specific periods of a bus cycle. these periods are referred to as time states. a typical bus cycle is composed of four consecutive time states: t 1 , t 2 , t 3 , and t 4 . wait states, which represent multiple t 3 states, are referred to as t w states. when no bus cycle is pending, an idle (t i ) state occurs. in the switching parameter descriptions, the multiplexed address is referred to as the ad address bus; the nonmultiplexed address is referred to as the a address bus. key to switching waveforms must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform input output invalid invalid 68 am186 tm er and am188 tm er microcontrollers data sheet draft alphabetical key to switching parameter symbols notes: the following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76. parameter symbol no. description parameter symbol no. description t arych 49 ardy resolution transition setup time t cldx 2 data in hold t arychl 51 ardy inactive holding time t clev 71 clkouta low to sden valid t arylcl 52 ardy setup time t clhav 62 hlda valid delay t avbl 87 a address valid to whb , wlb low t clrf 82 clkouta high to rfsh invalid t avch 14 ad address valid to clock high t clrh 27 rd inactive delay t avll 12 ad address valid to ale low t clrl 25 rd active delay t avrl 66 a address valid to rd low t clsh 4 status inactive delay t avwl 65 a address valid to wr low t clsl 72 clkouta low to sclk low t azrl 24 ad address float to rd active t clsry 48 srdy transition hold time t ch1ch2 45 clkouta rise time t cltmv 55 timer output delay t chav 68 clkouta high to a address valid t coaob 83 clkouta to clkoutb skew t chck 38 x1 high time t cvctv 20 control active delay 1 t chcl 44 clkouta high time t cvctx 31 control inactive delay t chcsv 67 clkouta high to lcs /ucs valid t cvdex 21 den inactive delay t chcsx 18 mcs /pcs inactive delay t cxcsx 17 mcs /pcs hold from command inactive t chctv 22 control active delay 2 t dvcl 1 data in setup t chcv 64 command lines valid delay (after float) t dvsh 75 data valid to sclk high t chcz 63 command lines float delay t dxdl 19 den inactive to dt/r low t chdx 8 status hold time t hvcl 58 hold setup t chlh 9 ale active delay t invch 53 peripheral setup time t chll 11 ale inactive delay t invcl 54 drq setup time t chrfd 79 clkouta high to rfsh valid t lcrf 86 lcs inactive to rfsh active delay t chsv 3 status active delay t lhav 23 ale high to address valid t cicoa 69 x1 to clkouta skew t lhll 10 ale width t cicob 70 x1 to clkoutb skew t llax 13 ad address hold from ale inactive t ckhl 39 x1 fall time t lock 61 maximum pll lock time t ckin 36 x1 period t lrll 84 lcs precharge pulse width t cklh 40 x1 rise time t resin 57 res setup time t cl2cl1 46 clkouta fall time t rfcy 85 rfsh cycle time t clarx 50 ardy active hold time t rhav 29 rd inactive to ad address active t clav 5 ad address valid delay t rhdx 59 rd high to data hold on ad bus t clax 6 address hold t rhlh 28 rd inactive to ale high t claz 15 ad address float delay t rlrh 26 rd pulse width t clch 43 clkouta low time t shdx 77 sclk high to spi data hold t clck 37 x1 low time t sldv 78 sclk low to spi data valid t clcl 42 clkouta period t srycl 47 srdy transition setup time t clclx 80 lcs inactive delay t whdex 35 wr inactive to den inactive t clcsl 81 lcs active delay t whdx 34 data hold after wr t clcsv 16 mcs /pcs active delay t whlh 33 wr inactive to ale high t cldox 30 data hold time t wlwh 32 wr pulse width t cldv 7 data valid delay am186 tm er and am188 tm er microcontrollers data sheet 69 draft numerical key to switching parameter symbols notes: the following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76. number parameter symbol description number parameter symbol description 1 t dvcl data in setup 43 t clch clkouta low time 2 t cldx data in hold 44 t chcl clkouta high time 3 t chsv status active delay 45 t ch1ch2 clkouta rise time 4 t clsh status inactive delay 46 t cl2cl1 clkouta fall time 5 t clav ad address valid delay 47 t srycl srdy transition setup time 6 t clax address hold 48 t clsry srdy transition hold time 7 t cldv data valid delay 49 t arych ardy resolution transition setup time 8 t chdx status hold time 50 t clarx ardy active hold time 9 t chlh ale active delay 51 t arychl ardy inactive holding time 10 t lhll ale width 52 t arylcl ardy setup time 11 t chll ale inactive delay 53 t invch peripheral setup time 12 t avll ad address valid to ale low 54 t invcl drq setup time 13 t llax ad address hold from ale inactive 55 t cltmv timer output delay 14 t avch ad address valid to clock high 57 t resin res setup time 15 t claz ad address float delay 58 t hvcl hold setup 16 t clcsv mcs /pcs active delay 59 t rhdx rd high to data hold on ad bus 17 t cxcsx mcs /pcs hold from command inactive 61 t lock maximum pll lock time 18 t chcsx mcs /pcs inactive delay 62 t clhav hlda valid delay 19 t dxdl den inactive to dt/r low 63 t chcz command lines float delay 20 t cvctv control active delay 1 64 t chcv command lines valid delay (after float) 21 t cvdex den inactive delay 65 t avwl a address valid to wr low 22 t chctv control active delay 2 66 t avrl a address valid to rd low 23 t lhav ale high to address valid 67 t chcsv clkouta high to lcs /ucs valid 24 t azrl ad address float to rd active 68 t chav clkouta high to address valid 25 t clrl rd active delay 69 t cicoa x1 to clkouta skew 26 t rlrh rd pulse width 70 t cicob x1 to clkoutb skew 27 t clrh rd inactive delay 71 t clev clkouta low to sden valid 28 t rhlh rd inactive to ale high 72 t clsl clkouta low to sclk low 29 t rhav rd inactive to ad address active 75 t dvsh data valid to sclk high 30 t cldox data hold time 77 t shdx sclk high to spi data hold 31 t cvctx control inactive delay 78 t sldv sclk low to spi data valid 32 t wlwh wr pulse width 79 t chrfd clkouta high to rfsh valid 33 t whlh wr inactive to ale high 80 t clclx lcs inactive delay 34 t whdx data hold after wr 81 t clcsl lcs active delay 35 t whdex wr inactive to den inactive 82 t clrf clkouta high to rfsh invalid 36 t ckin x1 period 83 t coaob clkouta to clkoutb skew 37 t clck x1 low time 84 t lrll lcs precharge pulse width 38 t chck x1 high time 85 t rfcy rfsh cycle time 39 t ckhl x1 fall time 86 t lcrf lcs inactive to rfsh active delay 40 t cklh x1 rise time 87 t avbl a address valid to whb , wlb low 42 t clcl clkouta period 70 am186 tm er and am188 tm er microcontrollers data sheet draft switching characteristics over commercial and industrial operating ranges read cycle (25 mhz and 33 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den , inta 1Cinta 0, wr , whb , and wlb signals. c if either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. preliminary parameter 25 mhz 33 mhz no. symbol description min max min max unit general timing requirements 1 t dvcl data in setup 10 8 ns 2 t cldx data in hold (c) 3 3 ns general timing responses 3 t chsv status active delay 0 20 0 15 ns 4 t clsh status inactive delay 0 20 0 15 ns 5 t clav ad address valid delay 0 20 0 15 ns 7 t cldv data valid delay 0 20 0 15 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 20 15 ns 10 t lhll ale width t clcl C10=30 t clcl C10=20 ns 11 t chll ale inactive delay 20 15 ns 12 t avll ad address valid to ale low (a) t clch t clch ns 13 t llax ad address hold from ale inactive (a) t chcl t chcl ns 14 t avch ad address valid to clock high 0 0 ns 15 t claz ad address float delay t clax =0 20 t clax =0 15 ns 16 t clcsv mcs /pcs active delay 0 20 0 15 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch t clch ns 18 t chcsx mcs /pcs inactive delay 0 20 0 15 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 20 t cvctv control active delay 1 (b) 0 20 0 15 ns 21 t cvdex den inactive delay 0 20 0 15 ns 22 t chctv control active delay 2 (b) 0 20 0 15 ns 23 t lhav ale high to address valid 15 10 ns read cycle timing responses 24 t azrl ad address float to rd active 0 0 ns 25 t clrl rd active delay 0 20 0 15 ns 26 t rlrh rd pulse width 2t clcl C15=65 2t clcl C15=45 ns 27 t clrh rd inactive delay 0 20 0 15 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C3 ns 29 t rhav rd inactive to ad address active (a) t clcl C10=30 t clcl C10=20 ns 59 t rhdx rd high to data hold on ad bus (c) 0 0 ns 66 t avrl a address valid to rd low 2t clcl C15=65 2t clcl C15=45 ns 67 t chcsv clkouta high to lcs /ucs valid 0 20 0 15 ns 68 t chav clkouta high to a address valid 0 20 0 15 ns am186 tm er and am188 tm er microcontrollers data sheet 71 draft switching characteristics over commercial and industrial operating ranges read cycle (40 mhz and 50 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den , i nta 1Cinta 0, wr , whb , and wlb signals. c if either specification 2 or specification 59 is met with respect to data hold time, the part will function correctly. preliminary parameter 40 mhz 50 mhz no. symbol description min max min max unit general timing requirements 1 t dvcl data in setup 5 5 ns 2 t cldx data in hold (c) 2 2 ns general timing responses 3 t chsv status active delay 0 12 0 10 ns 4 t clsh status inactive delay 0 12 0 10 ns 5 t clav ad address valid delay 0 12 0 10 ns 7 t cldv data valid delay 0 12 0 10 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 12 10 ns 10 t lhll ale width t clcl C5=20 15 ns 11 t chll ale inactive delay 12 10 ns 12 t avll ad address valid to ale low (a) t clch t clch ns 13 t llax ad address hold from ale inactive (a) t chcl t chcl ns 14 t avch ad address valid to clock high 0 0 ns 15 t claz ad address float delay t clax =0 12 0 10 ns 16 t clcsv mcs /pcs active delay 0 12 0 10 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch t clch ns 18 t chcsx mcs /pcs inactive delay 0 12 0 10 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 20 t cvctv control active delay 1 (b) 0 12 0 10 ns 21 t cvdex den inactive delay 0 14 0 14 ns 22 t chctv control active delay 2 (b) 0 12 0 10 ns 23 t lhav ale high to address valid 7.5 5 ns read cycle timing responses 24 t azrl ad address float to rd active 0 0 ns 25 t clrl rd active delay 0 10 0 10 ns 26 t rlrh rd pulse width 2t clcl C10=40 35 ns 27 t clrh rd inactive delay 0 12 0 10 ns 28 t rhlh rd inactive to ale high (a) t clch C2 t clch C2 ns 29 t rhav rd inactive to ad address active (a) t clcl C5=20 15 ns 59 t rhdx rd high to data hold on ad bus (c) 0 0 ns 66 t avrl a address valid to rd low 2 ? t clcl C10=40 2 ? t clcl C10=30 ns 67 t chcsv clkouta high to lcs /ucs valid 0 12 0 10 ns 68 t chav clkouta high to a address valid 0 10 0 10 ns 72 am186 tm er and am188 tm er microcontrollers data sheet draft read cycle waveforms clkouta t 1 t 2 t 3 t 4 t w s 2Cs 0 lcs , ucs ad15Cad0*, ad7Cad0** rd mcs 1Cmcs 0, pcs 6Cpcs 5, pcs 3Cpcs 0 address a19Ca0 den dt/r s6 bhe * ale 1 2 3 4 5 7 8 9 13 14 15 16 17 18 19 20 21 22 22 24 25 26 27 29 68 66 67 28 10 uzi s6 ao15Cao8** notes: * AM186ER microcontroller only ** am188er microcontroller only 59 23 4 11 s6 data status bhe address address 12 7 am186 tm er and am188 tm er microcontrollers data sheet 73 draft switching characteristics over commercial and industrial operating ranges write cycle (25 mhz and 33 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den , inta 1Cinta 0, wr , whb , and wlb signals. preliminary parameter 25 mhz 33 mhz no. symbol description min max min max unit general timing responses 3 t chsv status active delay 0 20 0 15 ns 4 t clsh status inactive delay 0 20 0 15 ns 5 t clav ad address valid delay 0 20 0 15 ns 7 t cldv data valid delay 0 20 0 15 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 20 15 ns 10 t lhll ale width t clcl C10=30 t clcl C10=20 ns 11 t chll ale inactive delay 20 15 ns 12 t avll ad address valid to ale low (a) t clch t clch ns 13 t llax ad address hold from ale inactive (a) t chcl t chcl ns 14 t avch ad address valid to clock high 0 0 ns 16 t clcsv mcs /pcs active delay 0 20 0 15 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch t clch ns 18 t chcsx mcs /pcs inactive delay 0 20 0 15 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 20 t cvctv control active delay 1 (b) 0 20 0 15 ns 23 t lhav ale high to address valid 15 10 ns write cycle timing responses 30 t cldox data hold time 0 0 ns 31 t cvctx control inactive delay (b) 0 20 0 15 ns 32 t wlwh wr pulse width 2t clcl C10=70 2t clcl C10=50 ns 33 t whlh wr inactive to ale high (a) t clch C2 t clch C2 ns 34 t whdx data hold after wr (a) t clcl C10=30 t clcl C10=20 ns 35 t whdex wr inactive to den inactive (a) t clch C3 t clch C5 ns 65 t avwl a address valid to wr low t clcl +t chcl C3 t clcl +t chcl C3 ns 67 t chcsv clkouta high to lcs /ucs valid 0 20 0 15 ns 68 t chav clkouta high to a address valid 0 20 0 15 ns 87 t avbl a address valid to whb, wlb low t chcl C3 20 t chcl C3 15 ns 74 am186 tm er and am188 tm er microcontrollers data sheet draft switching characteristics over commercial and industrial operating ranges write cycle (40 mhz and 50 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den , inta 1Cinta 0, wr , whb , and wlb signals. preliminary parameter 40 mhz 50 mhz no. symbol description min max min max unit general timing responses 3 t chsv status active delay 0 12 0 10 ns 4 t clsh status inactive delay 0 12 0 10 ns 5 t clav ad address valid delay 0 12 0 10 ns 7 t cldv data valid delay 0 12 0 10 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 12 10 ns 10 t lhll ale width t clcl C5=20 15 ns 11 t chll ale inactive delay 12 10 ns 12 t avll ad address valid to ale low (a) t clch t clch ns 13 t llax ad address hold from ale inactive (a) t chcl t chcl ns 14 t avch ad address valid to clock high 0 0 ns 16 t clcsv mcs /pcs active delay 0 12 0 10 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch t clch ns 18 t chcsx mcs /pcs inactive delay 0 12 0 10 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 20 t cvctv control active delay 1 (b) 0 12 0 10 ns 23 t lhav ale high to address valid 7.5 5 ns write cycle timing responses 30 t cldox data hold time 0 0 ns 31 t cvctx control inactive delay (b) 0 12 0 10 ns 32 t wlwh wr pulse width 2t clcl C10=40 35 ns 33 t whlh wr inactive to ale high (a) t clch C2 t clch C2 ns 34 t whdx data hold after wr (a) t clcl C10=15 12 ns 35 t whdex wr inactive to den inactive (a) t clch t clch ns 65 t avwl a address valid to wr low t clcl +t chcl C1.25 t clcl +t chcl C1.25 ns 67 t chcsv clkouta high to lcs /ucs valid 0 12 0 10 ns 68 t chav clkouta high to a address valid 0 10 0 10 ns 87 t avbl a address valid to whb, wlb low t chcl C1.25 12 t chcl C1.25 10 ns am186 tm er and am188 tm er microcontrollers data sheet 75 draft write cycle waveforms clkouta t 1 t 2 t 3 t 4 t w s 2Cs 0 status lcs , ucs address data ad15Cad0*, ad7Cad0** wr mcs 3Cmcs 0, pcs 6Cpcs 5, pcs 3Cpcs 0 address a19Ca0 den dt/r s6 s6 ale whb *, wlb wb bhe * bhe 3 4 5 7 8 9 10 11 12 13 14 16 17 18 19 67 68 65 35 31 20 30 34 32 31 33 uzi s6 20 31 87 ao15Cao8** address 23 4 notes: * AM186ER microcontroller only ** am188er microcontroller only 7 76 am186 tm er and am188 tm er microcontrollers data sheet draft switching characteristics over commercial and industrial operating ranges internal ram show read cycle (25 mhz and 33 mhz) switching characteristics over commercial and industrial operating ranges internal ram show read cycle (40 mhz and 50 mhz) preliminary parameter 25 mhz 33 mhz no. symbol description min max min max unit general timing responses 5 t clav ad address valid delay 0 20 0 15 ns 7 t cldv data valid delay 0 20 0 15 ns 9 t chlh ale active delay 20 15 ns 11 t chll ale inactive delay 20 15 ns read cycle timing responses 25 t clrl rd active delay 0 20 0 15 ns 27 t clrh rd inactive delay 0 20 0 15 ns 68 t chav clkouta high to a address valid 0 20 0 15 ns preliminary parameter 40 mhz 50 mhz no. symbol description min max min max unit general timing responses 5 t clav ad address valid delay 0 12 0 10 ns 7 t cldv data valid delay 0 12 0 10 ns 9 t chlh ale active delay 12 10 ns 11 t chll ale inactive delay 12 10 ns read cycle timing responses 25 t clrl rd active delay 0 10 0 10 ns 27 t clrh rd inactive delay 0 12 0 10 ns 68 t chav clkouta high to a address valid 0 10 0 10 ns am186 tm er and am188 tm er microcontrollers data sheet 77 draft internal ram show read cycle waveform clkouta t 1 t 2 t 3 t 4 ad15Cad0 rd address a19Ca0 ale data address 68 7 68 5 9 11 25 27 5 lcs, ucs mcs 3Cmcs 0, pcs 6Cpcs 5, pcs 3Cpcs 0 78 am186 tm er and am188 tm er microcontrollers data sheet draft switching characteristics over commercial and industrial operating ranges psram read cycle (25 mhz and 33 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a testing is performed with equal loading on referenced pins. b if either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. preliminary parameter 25 mhz 33 mhz no. symbol description min max min max unit general timing requirements 1 t dvcl data in setup 10 8 ns 2 t cldx data in hold (b) 3 3 ns general timing responses 5 t clav ad address valid delay 0 20 0 15 ns 7 t cldv data valid delay 0 20 0 15 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 20 15 ns 10 t lhll ale width t clcl C10=30 t clcl C10=20 ns 11 t chll ale inactive delay 20 15 ns 23 t lhav ale high to address valid 15 10 ns 80 t clclx lcs inactive delay 0 20 0 15 ns 81 t clcsl lcs active delay 0 20 0 15 ns 84 t lrll lcs precharge pulse width t clcl + t clch C3 t clcl + t clch C3 ns read cycle timing responses 24 t azrl ad address float to rd active 0 0 ns 25 t clrl rd active delay 0 20 0 15 ns 26 t rlrh rd pulse width 2t clcl C15=65 2t clcl C15=45 ns 27 t clrh rd inactive delay 0 20 0 15 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C3 ns 59 t rhdx rd high to data hold on ad bus (b) 0 0 ns 66 t avrl a address valid to rd low 2t clcl C15=65 2t clcl C15=45 ns 68 t chav clkouta high to a address valid 0 20 0 15 ns am186 tm er and am188 tm er microcontrollers data sheet 79 draft switching characteristics over commercial and industrial operating ranges psram read cycle (40 mhz and 50 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a testing is performed with equal loading on referenced pins. b if either specification 2 or specification 59 is met with respect to data hold time, the part will function correctly. preliminary parameter 40 mhz 50 mhz no. symbol description min max min max unit general timing requirements 1 t dvcl data in setup 5 5 ns 2 t cldx data in hold (b) 2 2 ns general timing responses 5 t clav ad address valid delay 0 12 0 10 ns 7 t cldv data valid delay 0 12 0 10 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 12 10 ns 10 t lhll ale width t clcl C5=20 15 ns 11 t chll ale inactive delay 12 10 ns 23 t lhav ale high to address valid 7.5 5 ns 80 t clclx lcs inactive delay 0 12 0 10 ns 81 t clcsl lcs active delay 0 12 0 10 ns 84 t lrll lcs precharge pulse width t clcl + t clch C1.25 t clcl + t clch C1 ns read cycle timing responses 24 t azrl ad address float to rd active 0 0 ns 25 t clrl rd active delay 0 10 0 10 ns 26 t rlrh rd pulse width 2t clcl C10=40 35 ns 27 t clrh rd inactive delay 0 12 0 10 ns 28 t rhlh rd inactive to ale high (a) t clch C1.25 t clch C1 ns 59 t rhdx rd high to data hold on ad bus (b) 0 0 ns 66 t avrl a address valid to rd low 2t clcl C10=40 2t clcl C10=30 ns 68 t chav clkouta high to a address valid 0 10 0 10 ns 80 am186 tm er and am188 tm er microcontrollers data sheet draft psram read cycle waveforms data clkouta t 1 t 2 t 3 t w lcs address ad15Cad0*, ad7Cad0** rd address a19Ca0 s6 s6 ale 1 2 5 7 8 9 11 24 25 26 27 68 66 28 10 s6 t 4 81 84 t 1 address 80 80 27 ao15Cao8** address notes: * AM186ER microcontroller only ** am188er microcontroller only 59 23 am186 tm er and am188 tm er microcontrollers data sheet 81 draft switching characteristics over commercial and industrial operating ranges psram write cycle (25 mhz and 33 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den , wr , whb and wlb signals. preliminary parameter 25 mhz 33 mhz no. symbol description min max min max unit general timing responses 5 t clav ad address valid delay 0 20 0 15 ns 7 t cldv data valid delay 0 20 0 15 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 20 15 ns 10 t lhll ale width t clcl C10=30 t clcl C10=20 ns 11 t chll ale inactive delay 20 15 ns 23 t lhav ale high to address valid 15 0 15 ns 20 t cvctv control active delay 1 (b) 0 20 10 ns 80 t clclx lcs inactive delay 0 20 0 15 ns 81 t clcsl lcs active delay 0 20 0 15 ns 84 t lrll lcs precharge pulse width t clcl + t clch C3 t clcl + t clch C3 write cycle timing responses 30 t cldox data hold time 0 0 ns 31 t cvctx control inactive delay (b) 0 20 0 15 ns 32 t wlwh wr pulse width 2t clcl C10=70 2t clcl C10=50 ns 33 t whlh wr inactive to ale high (a) t clch C2 t clch C2 ns 34 t whdx data hold after wr (a) t clcl C10=30 t clcl C10=20 ns 65 t avwl a address valid to wr low t clcl +t chcl C3 t clcl +t chcl C3 ns 68 t chav clkouta high to a address valid 0 20 0 15 ns 87 t avbl a address valid to whb, wlb low t chcl C3 20 t chcl C3 15 ns 82 am186 tm er and am188 tm er microcontrollers data sheet draft switching characteristics over commercial and industrial operating ranges psram write cycle (40 mhz and 50 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den , wr , whb and wlb signals. preliminary parameter 40 mhz 50 mhz no. symbol description min max min max unit general timing responses 5 t clav ad address valid delay 0 12 0 10 ns 7 t cldv data valid delay 0 12 0 10 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 12 10 ns 10 t lhll ale width t clcl C5=20 15 ns 11 t chll ale inactive delay 12 10 ns 20 t cvctv control active delay 1 (b) 0 12 0 10 ns 23 t lhav ale high to address valid 7.5 5 ns 80 t clclx lcs inactive delay 0 12 0 10 ns 81 t clcsl lcs active delay 0 12 0 10 ns 84 t lrll lcs precharge pulse width t clcl + t clch C1.25 t clcl + t clch C1 write cycle timing responses 30 t cldox data hold time 0 0 ns 31 t cvctx control inactive delay (b) 0 12 0 10 ns 32 t wlwh wr pulse width 2t clcl C10=40 35 ns 33 t whlh wr inactive to ale high (a) t clch C2 t clch C2 ns 34 t whdx data hold after wr (a) t clcl C10=15 12 ns 65 t avwl a address valid to wr low t clcl +t chcl C1.25 t clcl +t chcl C1.25 ns 68 t chav clkouta high to a address valid 0 10 0 10 ns 87 t avbl a address valid to whb, wlb low t chcl C1.25 18 t chcl C1.25 15 ns am186 tm er and am188 tm er microcontrollers data sheet 83 draft psram write cycle waveforms clkouta t 1 t 2 t 3 t 4 t w lcs address data ad15Cad0*, ad7Cad0** wr address a19Ca0 s6 s6 ale whb *, wlb * wb ** 5 7 8 9 10 11 68 65 20 30 34 32 33 t 1 31 20 80 84 81 87 80 31 ao15Cao8** address notes: * AM186ER microcontroller only ** am188er microcontroller only 23 data s6 84 am186 tm er and am188 tm er microcontrollers data sheet draft switching characteristics over commercial and industrial operating ranges psram refresh cycle (25 mhz and 33 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a testing is performed with equal loading on referenced pins. preliminary parameter 25 mhz 33 mhz no. symbol description min max min max unit general timing responses 9 t chlh ale active delay 20 15 ns 10 t lhll ale width t clcl C10=30 t clcl C10=20 ns 11 t chll ale inactive delay 20 15 ns read/write cycle timing responses 25 t clrl rd active delay 0 20 0 15 ns 26 t rlrh rd pulse width 2t clcl C15=65 2t clcl C15=45 ns 27 t clrh rd inactive delay 0 20 0 15 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C3 ns 80 t clclx lcs inactive delay 0 20 0 15 ns 81 t clcsl lcs active delay 0 20 0 15 ns refresh timing cycle parameters 79 t clrfd clkouta low to rfsh valid 0 20 0 15 ns 82 t clrf clkouta high to rfsh invalid 0 20 0 15 ns 85 t rfcy rfsh cycle time 6 x t clcl 6 x t clcl ns 86 t lcrf lcs inactive to rfsh active delay 2t clcl C3 2t clcl C3 ns am186 tm er and am188 tm er microcontrollers data sheet 85 draft switching characteristics over commercial and industrial operating ranges psram refresh cycle (40 mhz and 50 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a testing is performed with equal loading on referenced pins. preliminary parameter 40 mhz 50 mhz no. symbol description min max min max unit general timing responses 9 t chlh ale active delay 12 10 ns 10 t lhll ale width t clcl C5=20 15 ns 11 t chll ale inactive delay 12 10 ns read/write cycle timing responses 25 t clrl rd active delay 0 10 0 10 ns 26 t rlrh rd pulse width 2t clcl C10=40 35 ns 27 t clrh rd inactive delay 0 12 0 10 ns 28 t rhlh rd inactive to ale high (a) t clch C2 t clch C2 ns 80 t clclx lcs inactive delay 0 12 0 10 ns 81 t clcsl lcs active delay 0 12 0 10 ns refresh timing cycle parameters 79 t clrfd clkouta low to rfsh valid 0 12 0 10 ns 82 t clrf clkouta high to rfsh invalid 0 12 0 10 ns 85 t rfcy rfsh cycle time 6 x t clcl 6 x t clcl ns 86 t lcrf lcs inactive to rfsh active delay 2t clcl C1.25 2t clcl C1.25 ns 86 am186 tm er and am188 tm er microcontrollers data sheet draft psram refresh cycle waveforms clkouta t 1 t 2 t 3 t 4 t w * lcs rd address a19Ca0 ale 9 25 26 27 28 10 rfsh 11 t 1 79 85 82 80 81 86 * the period t w is fixed at three wait states for psram auto refresh only. 27 note: am186 tm er and am188 tm er microcontrollers data sheet 87 draft switching characteristics over commercial and industrial operating ranges interrupt acknowledge cycle (25 mhz and 33 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the inta 1Cinta 0 signals. c this parameter applies to the den and dt/r signals. preliminary parameter 25 mhz 33 mhz no. symbol description min max min max unit general timing requirements 1 t dvcl data in setup 10 8 ns 2 t cldx data in hold 3 3 ns general timing responses 3 t chsv status active delay 0 20 0 15 ns 4 t clsh status inactive delay 0 20 0 15 ns 7 t cldv data valid delay 0 20 0 15 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 20 15 ns 10 t lhll ale width t clcl C10=30 t clcl C10=20 ns 11 t chll ale inactive delay 20 15 ns 12 t avll ad address invalid to ale low (a) t clch t clch ns 15 t claz ad address float delay t clax =0 20 t clax =0 15 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 20 t cvctv control active delay 1 (b) 0 20 0 15 ns 21 t cvdex den inactive delay 0 20 0 15 ns 22 t chctv control active delay 2 (c) 0 20 0 15 ns 23 t lhav ale high to address valid 15 10 ns 31 t cvctx control inactive delay (b) 0 20 0 15 ns 68 t chav clkouta high to a address valid 0 20 0 15 ns 88 am186 tm er and am188 tm er microcontrollers data sheet draft switching characteristics over commercial operating ranges interrupt acknowledge cycle (40 mhz and 50 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the inta 1Cinta 0 signals. c this parameter applies to the den and dt/r signals. preliminary parameter 40 mhz 50 mhz no. symbol description min max min max unit general timing requirements 1 t dvcl data in setup 5 5 ns 2 t cldx data in hold 2 2 ns general timing responses 3 t chsv status active delay 0 12 0 10 ns 4 t clsh status inactive delay 0 12 0 10 ns 7 t cldv data valid delay 0 12 0 10 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 12 10 ns 10 t lhll ale width t clcl C5=20 15 ns 11 t chll ale inactive delay 12 12 ns 12 t avll ad address invalid to ale low (a) t clch t clch ns 15 t claz ad address float delay t clax =0 12 0 10 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 20 t cvctv control active delay 1 (b) 0 12 0 10 ns 21 t cvdex den inactive delay 0 14 0 14 ns 22 t chctv control active delay 2 (c) 0 12 0 10 ns 23 t lhav ale high to address valid 7.5 5 ns 31 t cvctx control inactive delay (b) 0 12 0 10 ns 68 t chav clkouta high to a address valid 0 10 0 10 ns am186 tm er and am188 tm er microcontrollers data sheet 89 draft interrupt acknowledge cycle waveforms clkouta t 1 t 2 t 3 t 4 t w s 2Cs 0 status ale ad15Cad0*, ad7Cad0** inta 1Cinta 0 den dt/r ptr address a19Ca0 s6 s6 bhe * bhe 8 1 2 3 4 7 9 10 11 12 15 19 20 22 22 22 68 31 (a) (b) (c) (d) s6 21 notes: * AM186ER microcontroller only ** am188er microcontroller only a the status bits become inactive in the state preceding t 4 . b the data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge transition occurs prior to t cldx (min). c this parameter applies to an interrupt acknowledge cycle that follows a write cycle. d if followed by a write cycle, this change occurs in the state preceding that write cycle. ao15Cao8** address 23 4 90 am186 tm er and am188 tm er microcontrollers data sheet draft switching characteristics over commercial and industrial operating ranges software halt cycle (25 mhz and 33 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den signal. switching characteristics over commercial and industrial operating ranges software halt cycle (40 mhz and 50 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a testing is performed with equal loading on referenced pins. b this parameter applies to the den signal. preliminary parameter 25 mhz 33 mhz no. symbol description min max min max unit general timing responses 3 t chsv status active delay 0 20 0 15 ns 4 t clsh status inactive delay 0 20 0 15 ns 5 t clav ad address invalid delay 0 20 0 15 ns 9 t chlh ale active delay 20 15 ns 10 t lhll ale width t clcl C10=30 t clcl C10=20 ns 11 t chll ale inactive delay 20 15 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 22 t chctv control active delay 2 (b) 0 20 0 15 ns 68 t chav clkouta high to a address invalid 0 20 0 15 ns preliminary parameter 40 mhz 50 mhz no. symbol description min max min max unit general timing responses 3 t chsv status active delay 0 12 0 10 ns 4 t clsh status inactive delay 0 12 0 10 ns 5 t clav ad address invalid delay 0 12 0 10 ns 9 t chlh ale active delay 12 10 ns 10 t lhll ale width t clcl C5=20 15 ns 11 t chll ale inactive delay 12 10 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 22 t chctv control active delay 2 (b) 0 12 0 10 ns 68 t chav clkouta high to a address invalid 0 10 0 10 ns am186 tm er and am188 tm er microcontrollers data sheet 91 draft software halt cycle waveforms clkouta t 1 t 2 t i t i s 2Cs 0 status ale invalid address s6, ad15Cad0*, ad7Cad0**, ao15-ao8** den dt/r invalid address a19Ca0 3 4 5 9 10 11 19 22 68 notes: * AM186ER microcontroller only ** am188er microcontroller only 92 am186 tm er and am188 tm er microcontrollers data sheet draft switching characteristics over commercial and industrial operating ranges clock (25 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a the specifications for clkin are applicable to the divide by two and times one modes. the times one mode should be used for operations from 16 mhz to 20 mhz. the times four mode should be used for operations above 20 mhz. preliminary parameter 25 mhz no. symbol description min max unit clkin requirements for times one mode 36 t ckin x1 period (a) 40 60 ns 37 t clck x1 low time (1.5 v) (a) 15 ns 38 t chck x1 high time (1.5 v) (a) 15 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) (a) 5 ns 40 t cklh x1 rise time (1.0 to 3.5 v) (a) 5 ns clkin requirements for divide by two mode 36 t ckin x1 period (a) 20 33 ns 37 t clck x1 low time (1.5 v) (a) 10 ns 38 t chck x1 high time (1.5 v) (a) 10 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) (a) 5 ns 40 t cklh x1 rise time (1.0 to 3.5 v) (a) 5 ns clkout timing 42 t clcl clkouta period 40 ns 43 t clch clkouta low time (c l =50 pf) 0.5t clcl C2=18 ns 44 t chcl clkouta high time (c l =50 pf) 0.5t clcl C2=18 ns 45 t ch1ch2 clkouta rise time (1.0 to 3.5 v) 3 ns 46 t cl2cl1 clkouta fall time (3.5 to 1.0 v) 3 ns 61 t lock maximum pll lock time 1 ms 69 t cicoa x1 to clkouta skew 20 ns 70 t cicob x1 to clkoutb skew 34 ns am186 tm er and am188 tm er microcontrollers data sheet 93 draft switching characteristics over commercial and industrial operating ranges clock (33 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a the times one mode should be used for operations from 16 mhz to 20 mhz. the times four mode should be used for operations above 20 mhz. preliminary parameter 33 mhz no. symbol description min max unit clkin requirements for times four mode 36 t ckin x1 period (a) 120 125 ns 37 t clck x1 low time (1.5 v) (a) 55 ns 38 t chck x1 high time (1.5 v) (a) 55 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) (a) 5 ns 40 t cklh x1 rise time (1.0 to 3.5 v) (a) 5 ns clkin requirements for times one mode 36 t ckin x1 period (a) 30 60 ns 37 t clck x1 low time (1.5 v) (a) 10 ns 38 t chck x1 high time (1.5 v) (a) 10 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) (a) 5 ns 40 t cklh x1 rise time (1.0 to 3.5 v) (a) 5 ns clkin requirements for divide by two mode 36 t ckin x1 period (a) 15 33 ns 37 t clck x1 low time (1.5 v) (a) 2.5 ns 38 t chck x1 high time (1.5 v) (a) 2.5 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) (a) 5 ns 40 t cklh x1 rise time (1.0 to 3.5 v) (a) 5 ns clkout timing 42 t clcl clkouta period 30 ns 43 t clch clkouta low time (c l =50 pf) 0.5t clcl C1.5=13.5 ns 44 t chcl clkouta high time (c l =50 pf) 0.5t clcl C1.5=13.5 ns 45 t ch1ch2 clkouta rise time (1.0 to 3.5 v) 3 ns 46 t cl2cl1 clkouta fall time (3.5 to 1.0 v) 3 ns 61 t lock maximum pll lock time 1 ms 69 t cicoa x1 to clkouta skew 20 ns 70 t cicob x1 to clkoutb skew 26 ns 94 am186 tm er and am188 tm er microcontrollers data sheet draft switching characteristics over commercial and industrial operating ranges clock (40 mhz and 50 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a the times one mode should be used for operations from 16 mhz to 20 mhz. the times four mode should be used for operations above 20 mhz. preliminary parameter 40 mhz 50 mhz no. symbol description min max min max unit clkin requirements for times four mode 36 t ckin x1 period (a) 100 125 80 125 ns 37 t clck x1 low time (1.5 v) (a) 45 35 ns 38 t chck x1 high time (1.5 v) (a) 45 35 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) (a) 5 5 ns 40 t cklh x1 rise time (1.0 to 3.5 v) (a) 5 5 ns clkin requirements for times one mode 36 t ckin x1 period (a) 25 60 not supported ns 37 t clck x1 low time (1.5 v) (a) 7.5 ns 38 t chck x1 high time (1.5 v) (a) 7.5 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) (a) 5 ns 40 t cklh x1 rise time (1.0 to 3.5 v) (a) 5 ns clkin requirements for divide by two mode 36 t ckin x1 period (a) 12.5 33 not supported ns 37 t clck x1 low time (1.5 v) (a) 1.25 ns 38 t chck x1 high time (1.5 v) (a) 1.25 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) (a) 5 ns 40 t cklh x1 rise time (1.0 to 3.5 v) (a) 5 ns clkout timing 42 t clcl clkouta period 25 20 ns 43 t clch clkouta low time (c l =50 pf) 0.5t clcl C1.25=11.25 0.5t clcl C1=9 ns 44 t chcl clkouta high time (c l =50 pf) 0.5t clcl C1.25=11.25 0.5t clcl C1=9 ns 45 t ch1ch2 clkouta rise time (1.0 to 3.5 v) 3 3 ns 46 t cl2cl1 clkouta fall time (3.5 to 1.0 v) 3 3 ns 61 t lock maximum pll lock time 1 1 ms 69 t cicoa x1 to clkouta skew 20 15 ns 70 t cicob x1 to clkoutb skew 24 21 ns am186 tm er and am188 tm er microcontrollers data sheet 95 draft clock waveformsactive mode clock waveformspower-save mode x1 x2 clkoutb clkouta (divide by one) 36 37 40 39 42 44 45 69 70 38 43 46 x1 clkouta (divide by four) x2 clkoutb ** clkoutb * notes: * the clkoutb output frequency (cbf) bit in the power save control register (pdcon) is set to 1. ** the clkoutb output frequency (cbf) bit in the power save control register (pdcon) is cleared to 0. 96 am186 tm er and am188 tm er microcontrollers data sheet draft switching characteristics over commercial and industrial operating ranges ready and peripheral timing (25 mhz and 33 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a this timing must be met to guarantee proper operation. b this timing must be met to guarantee recognition at the clock edge. switching characteristics over commercial and industrial operating ranges ready and peripheral timing (40 mhz and 50 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a this timing must be met to guarantee proper operation. b this timing must be met to guarantee recognition at the clock edge. preliminary parameter 25 mhz 33 mhz no. symbol description min max min max unit ready and peripheral timing requirements 47 t srycl srdy transition setup time (a) 10 8 ns 48 t clsry srdy transition hold time (a) 3 3 ns 49 t arych ardy resolution transition setup time (b) 10 8 ns 50 t clarx ardy active hold time (a) 4 4 ns 51 t arychl ardy inactive holding time 4 4 ns 52 t arylcl ardy setup time (a) 15 10 ns 53 t invch peripheral setup time (b) 10 8 ns 54 t invcl drq setup time (b) 10 8 ns peripheral timing responses 55 t cltmv timer output delay 20 15 ns preliminary parameter 40 mhz 50 mhz no. symbol description min max min max unit ready and peripheral timing requirements 47 t srycl srdy transition setup time (a) 5 5 ns 48 t clsry srdy transition hold time (a) 2 2 ns 49 t arych ardy resolution transition setup time (b) 5 5 ns 50 t clarx ardy active hold time (a) 3 3 ns 51 t arychl ardy inactive holding time 5 5 ns 52 t arylcl ardy setup time (a) 5 5 ns 53 t invch peripheral setup time (b) 5 5 ns 54 t invcl drq setup time (b) 5 5 ns peripheral timing responses 55 t cltmv timer output delay 12 10 ns am186 tm er and am188 tm er microcontrollers data sheet 97 draft synchronous ready waveforms asynchronous ready waveforms clkouta t w t w t w t 4 srdy (normally not- ready system) t 3 t w t w t 4 t 2 t 3 t w t 4 t 1 t 2 t 3 t 4 case 2 1 case 3 1 case 4 1 47 48 case 1 1 t 1 t 2 t 3 t w case 5 2 t 4 srdy (normally ready system) notes: 1. normally not-ready system. 2. normally ready system. clkouta t w t w t w t 4 ardy (normally not-ready system) t 3 t w t w t 4 t 2 t 3 t w t 4 t 1 t 2 t 3 t 4 case 2 1 case 3 1 case 4 1 ardy (normally ready system) 49 50 49 51 50 52 case 1 1 t 1 t 2 t 3 t w case 5 2 t 4 notes: 1. normally not-ready system. 2. normally ready system. 98 am186 tm er and am188 tm er microcontrollers data sheet draft peripheral waveforms clkouta tmrout1C tmrout0 drq1Cdrq0 int4Cint0, nmi, tmrin1Ctmrin0 53 54 55 am186 tm er and am188 tm er microcontrollers data sheet 99 draft switching characteristics over commercial and industrial operating ranges reset and bus hold (25 mhz and 33 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a this timing must be met to guarantee recognition at the next clock. switching characteristics over commercial and industrial operating ranges reset and bus hold (40 mhz and 50 mhz) notes: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. a this timing must be met to guarantee recognition at the next clock. preliminary parameter 25 mhz 33 mhz no. symbol description min max min max unit reset and bus hold timing requirements 5 t clav ad address valid delay 0 20 0 15 ns 15 t claz ad address float delay 0 20 0 15 ns 57 t resin res setup time 10 8 ns 58 t hvcl hold setup (a) 10 8 ns reset and bus hold timing responses 62 t clhav hlda valid delay 0 20 0 15 ns 63 t chcz command lines float delay 20 15 ns 64 t chcv command lines valid delay (after float) 20 15 ns preliminary parameter 40 mhz 50 mhz no. symbol description min max min max unit reset and bus hold timing requirements 5 t clav ad address valid delay 0 12 0 10 ns 15 t claz ad address float delay 0 12 0 10 ns 57 t resin res setup time 5 5 ns 58 t hvcl hold setup (a) 5 5 ns reset and bus hold timing responses 62 t clhav hlda valid delay 0 12 0 10 ns 63 t chcz command lines float delay 12 10 ns 64 t chcv command lines valid delay (after float) 12 10 ns 100 am186 tm er and am188 tm er microcontrollers data sheet draft reset waveforms signals related to reset waveforms x1 res clkouta 57 57 note: res must be held low for 1 ms during power-up to ensure proper device initialization. activating the pll will require 1 ms to achieve a stable clock. bhe /aden *, rfsh 2/aden *, s6/clksel1 * **, uzi /clksel 2** s 1/imdis *, and s 0/sren * res clkouta ad15Cad0 (186) ao15Cao8, ad7Cad0 (188) notes: * because bhe , rfsh 2, s6, uzi , s 1, and s 0 are not driven for 6.5 clocks after reset, their alternate functions can be asserted with external pulldown resistors. ** in divide by two mode and times one mode, s6/clksel 1 and uzi/clksel 2 must be held for 3 clock cycles after reset negates. ***in times four mode, s6/clksel 1 and uzi/clksel 2 must be held for 5 clock cycles after reset negates. s6/clksel 1***, uzi /clksel 2*** three-state three-state divide by two and times one modes times four mode three-state am186 tm er and am188 tm er microcontrollers data sheet 101 draft bus hold waveformsentering bus hold waveformsleaving clkouta t i t i t i ad15Cad0, den hlda a19Ca0, s6, rd , wr , bhe , dt/r , s 2-s 0 whb , wlb hold t 4 t i t i case 2 58 62 15 63 case 1 clkouta t i t i t 1 ad15Cad0, den hlda a19Ca0, s6, rd , wr , bhe , dt/r , s 2Cs 0 whb , wlb hold t i t 4 t 1 case 2 t i t i 58 62 64 5 case 1 102 am186 tm er and am188 tm er microcontrollers data sheet draft switching characteristics over commercial and industrial operating ranges synchronous serial interface (ssi) (25 mhz and 33 mhz) note: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. switching characteristics over commercial and industrial operating ranges synchronous serial interface (ssi) (40 mhz and 50 mhz) note: all timing parameters are measured at v cc /2 with 50 pf loading on clkouta, unless otherwise noted. all output test conditions are with c l =50 pf. for switching tests, v il =0.3 v and v ih =v cc C0.3 v. preliminary parameter 25 mhz 33 mhz no. symbol description min max min max unit synchronous serial port timing requirements 75 t dvsh data valid to sclk high 10 8 ns 77 t shdx sclk high to spi data hold 3 2 ns synchronous serial port timing responses 71 t clev clkouta low to sden1 or sden0 valid 20 0 15 ns 72 t clsl clkouta low to sclk low 20 0 15 ns 78 t sldv sclk low to data valid 20 0 15 ns preliminary parameter 40 mhz 50 mhz no. symbol description min max min max unit synchronous serial port timing requirements 75 t dvsh data valid to sclk high 5 5 ns 77 t shdx sclk high to spi data hold 2 2 ns synchronous serial port timing responses 71 t clev clkouta low to sden1 or sden0 valid 0 12 0 10 ns 72 t clsl clkouta low to sclk low 0 12 0 10 ns 78 t sldv sclk low to data valid 0 12 0 10 ns am186 tm er and am188 tm er microcontrollers data sheet 103 draft synchronous serial interface (ssi) waveforms note: sdata is bidirectional and used for either transmit (tx) or receive (rx). timing is shown separately for each case. clkouta sdata (rx) sclk sden1 or sden0 data 72 78 71 75 77 sdata (tx) data 72 104 am186 tm er and am188 tm er microcontrollers data sheet draft tqfp physical dimensions pql 100, trimmed and formed thin quad flat pack 1.00 ref. 1.60 max 11 ?13 11 ?13 0.50 bsc 100 1 1.35 1.45 15.80 16.20 13.80 14.20 15.80 16.20 13.80 14.20 0.17 0.27 16-038-pqt-2_ai pql100 9.3.96 lv notes: 1. all measurements are in millimeters, unless otherwise noted. 2. not to scale; for reference only. am186 tm er and am188 tm er microcontrollers data sheet 105 draft pqfp physical dimensions pqr 100, trimmed and formed plastic quad flat pack pin 100 pin 50 pin 30 pin 1 i.d. 17.00 17.40 12.35 ref 13.90 14.10 18.85 ref 19.90 20.10 23.00 23.40 0.25 min 2.70 2.90 0.65 basic 3.35 max seating plane 16-038-pqr-1_ah pqr100 dp92 6-20-96 lv pin 80 notes: 1. all measurements are in millimeters, unless otherwise noted. 2. not to scale; for reference only. 106 am186 tm er and am188 tm er microcontrollers data sheet draft am186?cc communications controller data sheet index-1 index a a17/pio7, 30 a18/pio8, 30 a19/pio9, 30 absolute maximum ratings, 60 active mode clock waveforms, 95 ad15Cad8, 30 ad7Cad0, 30 address bus AM186ER disable in effect, 42 normal operation, 42 am188er disable in effect, 43 ale, 31 alphabetic pio pin assignments, 36 ambient temperatures ambient, 62 pqfp with four-to-six layer board, 65 pqfp with two-layer board, 63 tqfp with four-to-six layer boards, 66 tqfp with two-layer board, 64 ao15Cao8, 30 application considerations, 14 ardy, 31 asynchronous ready waveforms, 97 asynchronous serial port, 56 b bhe /aden , 31 block diagram AM186ER, 2 am188er, 3 bus cycle encoding, 37 bus hold waveforms entering, 101 leaving, 101 bus interface unit, 41 bus operation, 41 byte write enables, 41 c chip-select low memory, 51 overlap, 51 timing, 49 unit, 49 upper memory, 51 chip-selects midrange memory, 51 peripheral, 52 clkouta, 31 clkoutb, 31 clock (25 mhz), 92 clock (33 mhz), 93 clock (40 and 50 mhz), 94 clock and power management, 44 clock frequencies minimum and maximum, 44 clock generation, 14 clock organization, 48 clock source crystal driven, 45 clock waveforms active mode, 95 power-save mode, 95 clocking modes, 39 commercial operating ranges, 60 comparison AM186ER and 80c186 microcontrollers, 15 crystal selecting, 45 crystal-driven clock source, 45 customer support, 13 documentation and literature, 13 hotline and web, 13 literature ordering, 13 third-party development support products, 13 web home page, 13 index-2 am186?cc communications controller data sheet d dc characteristics, 60 demonstration board products, 13 den /pio5, 31 description, 1 functional, 40 direct memory access, 54 dma AM186ER maximum transfer rates, 55 asynchronous serial port transfers, 55 channel control registers, 55C56 operation, 55 priority, 55C56 transfers through serial port, 56 unit block diagram, 56 documentation see customer support. drq1Cdrq0, 32 dt/r /pio4, 32 e emulator and debug modes, 52 internal memory disable, 52 show read enable, 52 external source clock, 45 f features 3.3-v operation with 5-v-tolerant i/o, 14 available native development tools, applications, and system software, 1 enhanced bus interface, 1 enhanced functionality, 1, 14 enhanced integrated peripherals, 1 enhanced performance, 14 faster access to memory and clock input modes, 1 integrated ram, 14 memory integration, 1 software-compatible, 1 x86 software compatibility, 14 four-pin interface, 57 functional description, 40 g gnd, 32 h hlda, 32 hold, 32 hotline and world wide web support, 13 i i/o circuitry, 59 i/o space, 40 industrial operating ranges, 60 initialization and processor reset, 48 input/output circuitry, 59 int0, 32 int1/select , 32 int2/inta 0/pio31, 33 int3/inta 1/irq, 33 int4/pio30, 33 interaction with external ram, 52 internal memory, 52 internal memory disable, 52 internal ram show read cycle waveform, 77 interrupt acknowledge cycle (25 and 33 mhz), 87 interrupt acknowledge cycle (40 and 50 mhz), 88 interrupt acknowledge cycle waveforms, 89 interrupt control unit, 53 programming, 53 j junction temperature calculation, 62 l lcs /once 0, 33 literature see customer support. logic diagram ardy and srdy synchronization, 49 low memory chip select, 51 low-voltage operation, 57 low-voltage standard, 59 am186?cc communications controller data sheet index-3 m mcs 2Cmcs 0, 34 mcs 3/rfsh /pio25, 33 memory interface, 14 example, 15 memory maps, 50 diagram, 50 memory organization, 40 midrange memory chip selects, 51 modes emulator and debug, 52 n nmi, 34 nonmultiplexed address bus, 41 numeric pio pin assignments, 36 o operating ranges, 60 commercial and industrial, 60 operation low-voltage, 57 ordering information, 4 oscillator configurations, 45 output enable, 41 p pcb, 44 reading and writing, 44 pcs 0/pio16, 34 pcs 1/pio17, 34 pcs 2/pio18, 34 pcs 3/pio19, 34 pcs 3Cpcs 0, 34 pcs 5/a1/pio3, 34 pcs 6/a2/pio2, 34 peripheral chip selects, 52 peripheral control block, 44 peripheral waveforms, 98 phase-locked loop, 44 pins a19Ca0, 30 ad15Cad8, 30 ad7Cad0, 30 ale, 31 alphabetic pio assignments, 36 ao15Cao8, 30 ardy, 31 bhe /aden , 31 clkouta, 31 clkoutb, 31 clocking modes, 39 den /pio5, 31 descriptions, 30 drq1Cdrq0, 32 dt/r /pio4, 32 gnd, 32 hlda, 32 hold, 32 int0, 32 int1/select , 32 int2/inta 0/pio31, 33 int3/inta 1/irq, 33 int4/pio30, 33 lcs /once 0, 33 mcs 2Cmcs 0, 34 mcs 3/rfsh /pio25, 33 nmi, 34 numeric pio assignments, 36 pcs 0/pio16, 34 pcs 1/pio17, 34 pcs 3Cpcs 0, 34 pcs 6/a2/pio2, 34 pio, 57 pio31Cpio0, 35 rd , 35 res , 35 rfsh 2/aden , 35 rxd/pio28, 35 s 0/sren , 37 s 1/imdis , 37 s 2, 35 s6/clksel 1/pio29, 37 sclk/pio20, 37 sdata/pio21, 37 sden0/pio22, 37 sden1/pio23, 37 srdy/pio6, 38 tmrin0/pio11, 38 tmrin1/pio0, 38 tmrout0/pio10, 38 tmrout1/pio1, 38 txd/pio27, 38 ucs /once 1, 38 used by emulators, 30 uzi /clksel 2/pio26, 38 vcc, 39 wb (am188er microcontroller only), 39 whb , 39 wlb (AM186ER microcontroller only), 39 wr , 39 x1, 39 x2, 39 pio31Cpio0, 35 plastic quad flat pack, 105 index-4 am186?cc communications controller data sheet pll, 44 power consumption calculation, 62 power savings, 59 power-save mode clock waveforms, 95 power-save operation, 48 pqfp connection diagram and pinouts AM186ER, 22 am188er, 25 pqfp physical dimensions, 105 pqfp pin assignments AM186ER sorted by pin name, 24 sorted by pin number, 23 am188er sorted by pin name, 27 sorted by pin number, 26 programmable i/o (pio) pins, 57 programming interrupt control unit, 53 ready and wait-state, 49 pseudo static ram support, 44 psram support, 44 psram read cycle (25 and 33 mhz), 78 psram read cycle (40 and 50 mhz), 79 psram read cycle waveforms, 80 psram refresh cycle (25 and 33 mhz), 84 psram refresh cycle (40 and 50 mhz), 85 psram refresh cycle waveforms, 86 psram write cycle waveforms, 83 psram write cycle (25 and 33 mhz), 81 psram write cycle (40 and 50 mhz), 82 r ram interaction with external, 52 rd , 35 read cycle waveforms, 72 ready and peripheral timing (25 and 33 mhz), 96 ready and peripheral timing (40 and 50 mhz), 96 ready and wait-state programming, 49 refresh control unit, 53 related documents, 13 res , 35 reset initialization and processor, 48 reset and bus hold (25 and 33 mhz), 99 reset and bus hold (40 and 50 mhz), 99 reset configuration register, 48 reset waveforms, 100 related signals, 100 revision history, 10 rfsh 2/aden , 35 rxd/pio28, 35 s s 0/sren , 37 s 1/imdis , 37 s 2, 35 s6/clksel 1/pio29, 37 sclk/pio20, 37 sdata/pio21, 37 sden0/pio22, 37 sden1/pio23, 37 serial ports dma transfers, 55 software halt cycle (25 and 33 mhz), 90 software halt cycle (40 and 50 mhz), 90 software halt cycle waveforms, 91 source clock external, 45 srdy/pio6, 38 ssi, 102 multiple read, 58 multiple write, 58 waveforms, 103 support, 13 switching characteristics clock (25 mhz), 92 clock (33 mhz), 93 clock (40 and 50 mhz), 94 commercial, 67 industrial, 67 internal ram show read cycle (25 and 33 mhz), 76 interrupt acknowledge cycle (25 and 33 mhz), 87 interrupt acknowledge cycle (40 and 50 mhz), 88 psram read cycle (25 and 33 mhz), 78 psram read cycle (40 and 50 mhz), 79 psram refresh cycle (25 and 33 mhz), 84 psram refresh cycle (40 and 50 mhz), 85 psram write cycle (25 and 33 mhz), 81 psram write cycle (40 and 50 mhz), 82 read cycle (25 and 33 mhz), 70 read cycle (40 and 50 mhz), 71 ready and peripheral timing (25 and 33 mhz), 96 ready and peripheral timing (40 and 50 mhz), 96 reset and bus hold (25 and 33 mhz), 99 reset and bus hold (40 and 50 mhz), 99 software halt cycle (25 and 33 mhz), 90 software halt cycle (40 and 50 mhz), 90 am186?cc communications controller data sheet index-5 synchronous serial interface (25 and 33 mhz), 102 synchronous serial interface (40 and 50 mhz), 102 write cycle (25 and 33 mhz), 72C73 write cycle (40 and 50 mhz), 74, 76 switching parameter symbols alphabetical key, 68 numerical key, 69 switching waveforms key, 67 synchronous ready waveforms, 97 synchronous serial interface, 56 multiple read, 58 multiple write, 58 synchronous serial interface (25 and 33 mhz), 102 synchronous serial interface (40 and 50 mhz), 102 synchronous serial interface waveforms, 103 t thermal characteristics, 61 thermal characteristics equations, 61 thermal resistance, 61 thin quad flat pack, 104 third-party development support products, 13 timer control unit, 53 tmrin0/pio11, 38 tmrin1/pio0, 38 tmrout0/pio10, 38 tmrout1/pio1, 38 tqfp connection diagram and pinouts AM186ER, 16 am188er, 19 tqfp package, 61 tqfp physical dimensions, 104 tqfp pin assignments AM186ER, 19 sorted by pin name, 18 sorted by pin number, 17 am188er sorted by pin name, 21 sorted by pin number, 20 two-component address, 40 txd/pio27, 38 typical ambient temperatures, 62 u ucs /once 1, 38 upper memory chip select, 51 uzi /clksel 2/pio26, 38 v vcc, 39 w watchdog timer, 54 waveform internal ram show read, 77 waveforms, 67 asynchronous ready, 97 bus hold entering, 101 leaving, 101 interrupt acknowledge cycle, 89 peripheral, 98 psram read cycle, 80 psram refresh cycle, 86 psram write cycle, 83 read cycle, 72 reset, 100 signals related to reset, 100 software halt cycle, 91 ssi, 103 synchronous ready, 97 synchronous serial interface, 103 write cycle, 75 wb (am188er microcontroller only), 39 whb , 39 wlb (AM186ER microcontroller only), 39 world wide web support, 13 wr , 39 write cycle waveforms, 75 www home page, 13 support, 13 x x1, 39 x2, 39 am186?cc communications controller data sheet trademarks ? 2000 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am386, am5 x 86, and am486 are registered trademarks, and am186, am188, e86, lan, and amd-k6 are trademarks of advanced micro devices, inc. fusione86 is a service mark of advanced micro devices, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies. disclaimer the contents of this document are provided in connection with advanced micro devices, inc. ("amd") products. amd makes no repre sentations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make c hanges to speci- fications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or oth erwise, to any in- tellectual property rights is granted by this publication. except as set forth in amd's standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, th e implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical impla nt into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's p roduct could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discont inue or make changes to its products at any time without notice. ? 2000 advanced micro devices, inc. all rights reserved. |
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